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    CHIP PACKAGE
    1.
    发明申请
    CHIP PACKAGE 有权
    芯片包装

    公开(公告)号：US20140004725A1

    公开(公告)日：2014-01-02

    申请号：US13674903

    申请日：2012-11-12

    Applicant: NOVATEK MICROELECTRONICS CORP.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01R12/51

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

    Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。

    Chip package
    2.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US09245857B2

    公开(公告)日：2016-01-26

    申请号：US14726613

    申请日：2015-06-01

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L23/40 ,  H01L23/60 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H02H9/02

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

    Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

    Power Rail Clamp Circuit
    3.
    发明申请
    Power Rail Clamp Circuit 审中-公开

    公开(公告)号：US20180159318A1

    公开(公告)日：2018-06-07

    申请号：US15372363

    申请日：2016-12-07

    Applicant: NOVATEK Microelectronics Corp.

    Inventor： Jie-Ting Chen ,  Chun-Yu Lin ,  Ming-Dou Ker ,  Ju-Lin Huang ,  Tzu-Chiang Lin ,  Tzu-Chien Tzeng

    IPC: H02H9/04 ,  H02H1/04

    CPC classification number: H02H9/04 ,  H02H1/04 ,  H02H9/041

    Abstract: A power rail clamp circuit is coupled between a system power supply and a ground for alleviating an electrostatic discharge effect. The power rail clamp circuit includes a first conduction circuit, a second conduction circuit, an AND gate module and a switch module. The AND gate module receives a first conduction signal generated by the first conduction circuit and a second conduction signal generated by the second conduction circuit to generate an enabling signal. The switch module conducts the power rail clamp circuit according to the enabling signal, to process an electrostatic discharge operation. The first conduction circuit is operated to prevent a high voltage value of the system power supply, and the second conduction circuit is operated to prevent a short initiation period of the system power supply.

    CHIP PACKAGE
    4.
    发明申请
    CHIP PACKAGE 审中-公开
    芯片包装

    公开(公告)号：US20150262943A1

    公开(公告)日：2015-09-17

    申请号：US14726613

    申请日：2015-06-01

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/60 ,  H02H9/02 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body. The package body includes a core circuit and an electrostatic discharge protection circuit. A first connection terminal electrically is connected to the core circuit. A second connection terminal electrically is connected to the electrostatic discharge protection circuit. A first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection terminal and a third connection terminal. A first lead electrically connects the second connection terminal and an external circuit. A second lead electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are substantially separate.

    Abstract translation: 芯片封装结构包括封装体。 封装体包括核心电路和静电放电保护电路。 第一连接端子电连接到核心电路。 第二连接端子电连接到静电放电保护电路。 电连接到静电放电保护电路的第一互连结构，第二连接端子和第三连接端子。 第一引线将第二连接端子和外部电路电连接。 第二引线电连接第一连接端子和第三连接端子。 第二个领先者和第一个领先者基本上是分开的。

    Chip package
    5.
    发明授权
    Chip package 有权
    芯片封装

    公开(公告)号：US09048243B2

    公开(公告)日：2015-06-02

    申请号：US13674903

    申请日：2012-11-12

    Applicant: Novatek Microelectronics Corp.

    Inventor： Jhih-Siou Cheng ,  Tzu-Chiang Lin ,  Chia-En Wu ,  Chun-Yung Cho ,  Cheng-Hung Chen ,  Ju-Lin Huang

    IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/60 ,  H05K9/00 ,  H01L25/065

    CPC classification number: H01L23/60 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16137 ,  H01L2224/16195 ,  H01L2924/0002 ,  H02H9/02 ,  H05K9/0067 ,  H01L2924/00

    Abstract: A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.

    Abstract translation: 芯片封装结构包括封装体，第一引线和第二引线。 嵌入在封装体内的元件包括具有至少一个第一连接端子，至少一个ESD保护电路的至少一个第二连接端子，至少一个第三连接端子和至少一个互连结构的芯电路。 互连结构电连接到第二连接端子和第三连接端子。 封装主体上的第一引线电连接到第二连接端子和外部电路。 封装体上的第二引线电连接第一连接端子和第三连接端子。 第二个引线和第一个引线在结构上是分开的。

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