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公开(公告)号：US09727113B2
公开(公告)日：2017-08-08
申请号：US14458014
申请日：2014-08-12
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
CPC classification number: G06F1/3203 , G06F1/3287 , G06F15/8061 , G06T1/20 , Y02D10/171
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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公开(公告)号：US20180101746A1
公开(公告)日：2018-04-12
申请号：US15835926
申请日：2017-12-08
Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
Inventor： Cormac Brick , Brendan Barry , Fergal Connor , David Moloney
CPC classification number: G06K9/4604 , G06K9/00986
Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
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公开(公告)号：US09910675B2
公开(公告)日：2018-03-06
申请号：US14458052
申请日：2014-08-12
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
CPC classification number: G06F9/3867 , G06F13/28 , G06F15/8092 , G06T1/20
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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公开(公告)号：US20180246725A1
公开(公告)日：2018-08-30
申请号：US15900368
申请日：2018-02-20
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
CPC classification number: G06F9/3867 , G06F13/28 , G06F15/8092 , G06T1/20
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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Patent Agency Ranking
公开(公告)号：US09842271B2
公开(公告)日：2017-12-12
申请号：US14283603
申请日：2014-05-21
Applicant: Linear Algebra Technologies Limited
Inventor： Cormac Brick , Brendan Barry , Fergal Connor , David Moloney
CPC classification number: G06K9/4604 , G06K9/00986
Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
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公开(公告)号：US09196017B2
公开(公告)日：2015-11-24
申请号：US14081462
申请日：2013-11-15
Applicant: Linear Algebra Technologies Limited
Inventor： David Donohoe , Brendan Barry , David Moloney , Richard Richmond , Fergal Connor
CPC classification number: G06T5/002 , G06T2200/28 , G06T2207/20182 , H04N5/21 , H04N5/217
Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.
Abstract translation: 所公开的实施例包括在半导体集成芯片中实现的装置。 该装置被配置为在图像的第一块上操作包括第一功能和第二功能的复合功能。 该装置包括第一功能操作器，其被配置为对该组像素值操作第一功能以提供第一处理的像素值组。 该装置还包括延迟系统，其被配置为在预定时间段内保持第一经处理的像素值组以提供延迟处理的像素值组。 该装置还包括第二功能操作器，其被配置为在至少第二处理的像素组和延迟处理的组上操作第二功能以确定复合功能的输出。
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公开(公告)号：US10572252B2
公开(公告)日：2020-02-25
申请号：US15382467
申请日：2016-12-16
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Fergal Connor , Martin O'Riordan , David Moloney , Sean Power
IPC: G06F9/30 , G06F1/3203 , G06F9/38 , G06F15/80 , G06F1/32 , G06F1/3234 , G06F1/3287
Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
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公开(公告)号：US10521238B2
公开(公告)日：2019-12-31
申请号：US15900368
申请日：2018-02-20
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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公开(公告)号：US10001993B2
公开(公告)日：2018-06-19
申请号：US14457929
申请日：2014-08-12
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Fergal Connor , Martin O'Riordan , David Moloney , Sean Power
CPC classification number: G06F9/30036 , G06F1/32 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F9/30 , G06F9/3001 , G06F9/30032 , G06F9/3004 , G06F9/30058 , G06F9/30072 , G06F9/30149 , G06F9/3804 , G06F9/3816 , G06F9/3822 , G06F15/8053 , Y02D10/152 , Y02D10/171
Abstract: A vector processor is disclosed including a variety of variable-length instructions. Computer-implemented methods are disclosed for efficiently carrying out a variety of operations in a time-conscious, memory-efficient, and power-efficient manner. Methods for more efficiently managing a buffer by controlling the threshold based on the length of delay line instructions are disclosed. Methods for disposing multi-type and multi-size operations in hardware are disclosed. Methods for condensing look-up tables are disclosed. Methods for in-line alteration of variables are disclosed.
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