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公开(公告)号：US20180101746A1
公开(公告)日：2018-04-12
申请号：US15835926
申请日：2017-12-08
Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
Inventor： Cormac Brick , Brendan Barry , Fergal Connor , David Moloney
CPC classification number: G06K9/4604 , G06K9/00986
Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
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公开(公告)号：US09910675B2
公开(公告)日：2018-03-06
申请号：US14458052
申请日：2014-08-12
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
CPC classification number: G06F9/3867 , G06F13/28 , G06F15/8092 , G06T1/20
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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公开(公告)号：US20190156141A1
公开(公告)日：2019-05-23
申请号：US16098092
申请日：2017-06-06
Applicant: Linear Algebra Technologies Limited
Inventor： David Moloney , Alireza Dehghani
Abstract: Methods, systems, apparatus and articles of manufacture are disclosed herein to improve image classification with boundary-bitmaps. An example disclosed apparatus includes a silhouette engine to identify a foreground silhouette within the image, generate a bounding box based on borders of the foreground silhouette, and generate an encoded silhouette matrix which identifies cells of a foreground and cells of a background, a convolution cell selector to convolve the encoded silhouette matrix to generate a convoluted bitmap matrix, and a filter cell selector to improve image classification efficiency by identifying eligible blocks of the convoluted bitmap matrix by retaining first respective cells of the convoluted bitmap matrix that satisfy a cell retention threshold, and removing second respective cells of the convoluted bitmap matrix that do not satisfy the cell retention threshold.
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公开(公告)号：US09842271B2
公开(公告)日：2017-12-12
申请号：US14283603
申请日：2014-05-21
Applicant: Linear Algebra Technologies Limited
Inventor： Cormac Brick , Brendan Barry , Fergal Connor , David Moloney
CPC classification number: G06K9/4604 , G06K9/00986
Abstract: The present application provides a method of corner detection and an image processing system for detecting corners in an image. The preferred implementation is in software using enabling and reusable hardware features in the underlying vector processor architecture. The advantage of this combined software and programmable processor datapath hardware is that the same hardware used for the FAST algorithm can also be readily applied to a variety of other computational tasks, not limited to image processing.
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公开(公告)号：US09196017B2
公开(公告)日：2015-11-24
申请号：US14081462
申请日：2013-11-15
Applicant: Linear Algebra Technologies Limited
Inventor： David Donohoe , Brendan Barry , David Moloney , Richard Richmond , Fergal Connor
CPC classification number: G06T5/002 , G06T2200/28 , G06T2207/20182 , H04N5/21 , H04N5/217
Abstract: The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.
Abstract translation: 所公开的实施例包括在半导体集成芯片中实现的装置。 该装置被配置为在图像的第一块上操作包括第一功能和第二功能的复合功能。 该装置包括第一功能操作器，其被配置为对该组像素值操作第一功能以提供第一处理的像素值组。 该装置还包括延迟系统，其被配置为在预定时间段内保持第一经处理的像素值组以提供延迟处理的像素值组。 该装置还包括第二功能操作器，其被配置为在至少第二处理的像素组和延迟处理的组上操作第二功能以确定复合功能的输出。
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Patent Agency Ranking
公开(公告)号：US11037020B2
公开(公告)日：2021-06-15
申请号：US16271779
申请日：2019-02-08
Applicant: LINEAR ALGEBRA TECHNOLOGIES LIMITED
Inventor： David Moloney , Alireza Dehghani
Abstract: Systems and methods are provided for image classification using histograms of oriented gradients (HoG) in conjunction with a trainer. The efficiency of the process is greatly increased by first establishing a bitmap which identifies a subset of the pixels in the HoG window as including relevant foreground information, and limiting the HoG calculation and comparison process to only the pixels included in the bitmap.
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公开(公告)号：US10460704B2
公开(公告)日：2019-10-29
申请号：US15088816
申请日：2016-04-01
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , David Moloney
IPC: G06T15/00 , G09G5/391 , G02B27/01 , G06F3/01 , G09G5/00 , H04N19/597 , H04N19/132 , H04N19/17 , H04N19/167 , H04N19/426 , H04N13/344 , H04N13/383 , H04N13/398
Abstract: Systems and methods are provided for rendering of a dual eye-specific display. The system tracks the user's eye movements and/or positions, in some implementations, based on electroencephalography (EEG) of the user, to correctly label the central (foveal) and peripheral (extra-foveal) areas of the display. Foveal data is fully rendered while extra-foveal data is reduced in resolution and, in some implementations, shared between the two displays.
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公开(公告)号：US20180349147A1
公开(公告)日：2018-12-06
申请号：US15900327
申请日：2018-02-20
Applicant: Linear Algebra Technologies Limited
Inventor： David Moloney , Richard Richmond , David Donohoe , Brendan Barry
CPC classification number: G06F9/3885 , G06T1/20 , G06T1/60 , G09G5/363 , G09G5/397 , G09G2360/08 , G09G2360/122 , G09G2360/126
Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
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公开(公告)号：US20180246725A1
公开(公告)日：2018-08-30
申请号：US15900368
申请日：2018-02-20
Applicant: Linear Algebra Technologies Limited
Inventor： Brendan Barry , Richard Richmond , Fergal Connor , David Moloney
CPC classification number: G06F9/3867 , G06F13/28 , G06F15/8092 , G06T1/20
Abstract: The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
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公开(公告)号：US10360040B2
公开(公告)日：2019-07-23
申请号：US15900327
申请日：2018-02-20
Applicant: Linear Algebra Technologies Limited
Inventor： David Moloney , Richard Richmond , David Donohoe , Brendan Barry
Abstract: The present application relates generally to a parallel processing device. The parallel processing device can include a plurality of processing elements, a memory subsystem, and an interconnect system. The memory subsystem can include a plurality of memory slices, at least one of which is associated with one of the plurality of processing elements and comprises a plurality of random access memory (RAM) tiles, each tile having individual read and write ports. The interconnect system is configured to couple the plurality of processing elements and the memory subsystem. The interconnect system includes a local interconnect and a global interconnect.
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