公开(公告)号：US20190042412A1

公开(公告)日：2019-02-07

申请号：US15757727

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Jianghong Du ,  Yong Jiang ,  Lei Shen ,  Yuanyuan Li ,  Ruijia Li ,  Lingyi Kong

IPC: G06F12/084

Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

公开(公告)号：US11068401B2

公开(公告)日：2021-07-20

申请号：US15757727

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Jianghong Du ,  Yong Jiang ,  Lei Shen ,  Yuanyuan Li ,  Ruijia Li ,  Lingyi Kong

IPC: G06F12/084

Abstract: Methods and apparatus to improve shared memory efficiency are described. In an embodiment, a first version of a code to access one or more registers as shared local memory is compiled. A second version of the same code is also compiled to access a cache as the shared local memory. The first version of the code is executed in response to comparison of a work group size of the code with a threshold value. Other embodiments are also disclosed and claimed.

公开(公告)号：US10331496B2

公开(公告)日：2019-06-25

申请号：US15019943

申请日：2016-02-09

Applicant: INTEL CORPORATION

Inventor： Yong Jiang ,  Ruijia Li ,  Lei Shen

IPC: G06F9/45 ,  G06F9/50 ,  G06F8/52 ,  G06F9/48 ,  G06F9/455

Abstract: Systems, apparatus, articles, and methods are described including operations for runtime dispatching among a heterogeneous group of processors.

公开(公告)号：US09247244B2

公开(公告)日：2016-01-26

申请号：US13783006

申请日：2013-03-01

Applicant: Intel Corporation

Inventor： Ruijia Li ,  Chun Xi Chen

IPC: H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04N7/173 ,  G06F3/048 ,  H04N19/136 ,  H04N19/37 ,  H04N19/40

CPC classification number: H04N19/136 ,  H04N19/37 ,  H04N19/40

Abstract: A video system includes a sensitive-information generator to generate a definition of sensitive information parts (SIP) areas. The video system also includes a transcoder to transcode the SIP areas at a higher bit rate than non-SIP areas in the frames based on bandwidth available for transmitting the transcoded frames. The SIP areas are generated statically or dynamically. The video system adapts to various network conditions and utilizes the bandwidth efficiently to deliver the sensitive information of high quality and to enhance the user experience.