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公开(公告)号：US11080212B2
公开(公告)日：2021-08-03
申请号：US16835241
申请日：2020-03-30
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
IPC: G06F13/42 , G06F13/16 , G06F1/12 , G06F13/40 , H04L12/933 , H04L12/741
Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
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公开(公告)号：US20210117350A1
公开(公告)日：2021-04-22
申请号：US17134242
申请日：2020-12-25
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L12/933 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US10061719B2
公开(公告)日：2018-08-28
申请号：US14583147
申请日：2014-12-25
Applicant: Intel Corporation
Inventor： Brian S. Morris , Jeffrey C. Swanson , Bill Nale , Robert G. Blankenship , Jeff Willey , Eric L. Hendrickson
CPC classification number: G06F13/1663 , G06F13/1673 , G11C5/04 , G11C7/10
Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.
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公开(公告)号：US20170308497A1
公开(公告)日：2017-10-26
申请号：US15393518
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson
CPC classification number: G06F13/4221 , G06F13/4265 , H03M13/09
Abstract: A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.
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公开(公告)号：US11741030B2
公开(公告)日：2023-08-29
申请号：US17134242
申请日：2020-12-25
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , H04L9/0662 , H04L49/15 , G06F8/73 , G06F13/4273 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L12/4641 , H04L45/74 , Y02D10/00 , Y02D30/00
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US20190391939A1
公开(公告)日：2019-12-26
申请号：US16285035
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F12/0808 , H04L9/06 , G06F13/42 , G06F11/10 , G06F13/40 , G06F1/3287 , G06F9/445 , G06F9/46 , G06F12/0831 , G06F12/0806 , G06F9/30 , G06F8/77 , G06F8/71 , G06F12/0815 , G06F12/0813 , H04L12/933
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
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公开(公告)号：US10365965B2
公开(公告)日：2019-07-30
申请号：US15706191
申请日：2017-09-15
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
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公开(公告)号：US20180143937A1
公开(公告)日：2018-05-24
申请号：US15692613
申请日：2017-08-31
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
IPC: G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F9/445 , G06F9/46 , G06F12/0806 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/40 , H04L12/933
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
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公开(公告)号：US20170123894A1
公开(公告)日：2017-05-04
申请号：US15264680
申请日：2016-09-14
Applicant: Intel Corporation
Inventor： Jeff Willey , Robert G. Blankenship , Jeffrey C. Swanson , Robert J. Safranek
CPC classification number: G06F11/1004 , G06F13/4221 , G06F13/4282 , G06F2213/0026 , H03M13/09 , H04L12/4641
Abstract: Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.
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公开(公告)号：US20170109296A1
公开(公告)日：2017-04-20
申请号：US15393427
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Jeff Willey , Robert G. Blankenship
CPC classification number: G06F13/161 , G06F1/12 , G06F13/1673 , G06F13/4004 , G06F13/4068 , G06F13/4221 , H04L45/74 , H04L49/15
Abstract: A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
