公开(公告)号：US09154157B2

公开(公告)日：2015-10-06

申请号：US13629467

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhugani

IPC: G06F17/30 ,  H03M7/30

CPC classification number: H03M7/30

Abstract: Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data. The search unit may use a look-up table to identify appropriate compression or decompression symbols. The look-up table may be populated with a table derived using the variable length coding symbols of a sequence of vertices to be compressed or extracted from a received data stream to be decompressed. A comparator and a finite state machine may be implemented in the search unit to facilitate traversal of the look-up table.

Abstract translation: 用处理器核心实现的搜索单元来加速压缩和解压缩的系统和方法。 根据实施例，可以实现搜索单元以对输入的数据流执行压缩或解压缩。 搜索单元可以使用查找表来标识适当的压缩或解压缩符号。 查找表可以使用将要从要被解压缩的接收数据流压缩或提取的顶点序列的可变长度编码符号导出的表来填充。 可以在搜索单元中实现比较器和有限状态机，以便于遍历查找表。

公开(公告)号：US20150228091A1

公开(公告)日：2015-08-13

申请号：US14693056

申请日：2015-04-22

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G06T11/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20170242700A1

公开(公告)日：2017-08-24

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621 ,  Y02D10/13

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US09076254B2

公开(公告)日：2015-07-07

申请号：US14054933

申请日：2013-10-16

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G09G5/00 ,  G06T11/00 ,  G06F17/16 ,  G06T1/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20130297878A1

公开(公告)日：2013-11-07

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US10152325B2

公开(公告)日：2018-12-11

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F9/54

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US09678750B2

公开(公告)日：2017-06-13

申请号：US13795234

申请日：2013-03-12

Applicant: Intel Corporation

Inventor： Mikhail Smelyanskiy ,  Victor Lee ,  Christopher Hughes ,  Daehyun Kim ,  Yen-Kuang Chen ,  Changkyu Kim ,  Jatin Chhugani ,  Anthony D. Nguyen ,  Sanjeev Kumar

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06T5/40 ,  H04N1/407 ,  G06K9/62

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3885 ,  G06K9/6212 ,  G06T5/40 ,  H04N1/4074

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

公开(公告)号：US09069671B2

公开(公告)日：2015-06-30

申请号：US14337174

申请日：2014-07-21

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US08799577B2

公开(公告)日：2014-08-05

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US09563425B2

公开(公告)日：2017-02-07

申请号：US13687918

申请日：2012-11-28

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38 ,  G06F12/08 ,  G06F9/54

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621 ,  Y02D10/13

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

Abstract translation: 说明和逻辑提供推送缓冲区复制和存储功能。 一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。 响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据 当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。