公开(公告)号：US20220300692A1

公开(公告)日：2022-09-22

申请号：US17835323

申请日：2022-06-08

Applicant: Intel Corporation

Inventor： Jin Yan ,  Adam Norman ,  Min Suet Lim ,  Mackenzie Norman ,  Hong Cheah Ho ,  Jianfang Zhu ,  Miaomiao Ma

IPC: G06F30/392 ,  G06F30/398

Abstract: Systems, apparatuses and methods may provide for technology that identifies a plurality of functional blocks in a circuit, wherein each functional block includes a plurality of components, conducts one or more passes of a first optimization loop to determine candidate aspect ratios for the functional blocks based on size data associated with the components, and conducts, within the one or more passes of the first optimization loop, one or more passes of a second optimization loop to determine candidate floorplan data for the circuit based on the candidate aspect ratios.

公开(公告)号：US20230385507A1

公开(公告)日：2023-11-30

申请号：US18326772

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Adam Norman ,  Min Suet Lim ,  Miaomiao Ma ,  Mackenzie Norman ,  John Vu ,  Ching Leong Ooi ,  Eng Same Tan ,  Luis Carlos Alvarez Mata

IPC: G06F30/392 ,  G06F30/27

CPC classification number: G06F30/392 ,  G06F30/27

Abstract: Systems, apparatuses and methods may provide for technology that receives parameter results and scores of one or more local sessions with respect to subcircuit components in a bounded area, aggregates the parameter results and scores, and generates a global placement model based on an output of the aggregated parameter results and scores.

公开(公告)号：US20240202419A1

公开(公告)日：2024-06-20

申请号：US18538409

申请日：2023-12-13

Applicant: Intel Corporation

Inventor： Miaomiao Ma ,  Adam Norman ,  Jianfang Olena Zhu ,  Mackenzie Norman ,  Mark Gallina ,  Pei Chun Ch'ng ,  Xia Zhu ,  Jagadeesh Radhakrishnan ,  Soon Khiang Toh ,  Omer Vikinski ,  Slade Morgan

IPC: G06F30/392 ,  G06F30/27 ,  G06F115/02 ,  G06F119/08

CPC classification number: G06F30/392 ,  G06F30/27 ,  G06F2115/02 ,  G06F2119/08

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of transient thermal responses for a corresponding plurality of power source locations on a semiconductor die, obtains corner block list (CBL) representations associated with a plurality of candidate floorplans, and conducts an artificial intelligence (AI) based search of the CBL representations, wherein an output of the AI based search is one or more suggested floorplans having a transient thermal response that is below a thermal threshold.

公开(公告)号：US20220114136A1

公开(公告)日：2022-04-14

申请号：US17558172

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Ivan Chen ,  Barnes Cooper ,  Jianwei Dai ,  Martin Dixon ,  Kristoffer Fleming ,  Mark Gallina ,  Duncan Glendinning ,  Deepak Samuel Kirubakaran ,  Chia-Hung S. Kuo ,  Yifan Li ,  Adam Norman ,  Michael Rosenzweig ,  Kai P Wang ,  Jin Yan ,  Virendra Vikramsinh Adsure

IPC: G06F15/78 ,  G06F9/445

Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

公开(公告)号：US09172428B2

公开(公告)日：2015-10-27

申请号：US13931721

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Dawson Kesling ,  Adam Norman ,  Alberto Alcocer Ochoa ,  Eduardo Alban

IPC: H04B3/00 ,  H04B3/46 ,  H04L12/26

CPC classification number: H04B3/46 ,  H04L43/0823

Abstract: Techniques for determining the spectral content of a data bus are described herein. An example of a device in accordance with the present techniques includes a data bus comprising one or more signal lines, a first phasor generator, and a second phasor generator. The first phasor generator obtains a first data value based on the data to be transmitted over the data bus and generates a first phasor. The second phasor generator obtains a second data value based on the data to be transmitted over the data bus and generates a second phasor. The sum of the first phasor and the second phasor indicate, at least in part, the spectral content of the data to be transmitted over the data bus.

Abstract translation: 本文描述了用于确定数据总线的频谱内容的技术。 根据本技术的装置的示例包括包括一个或多个信号线的数据总线，第一相量发生器和第二相量发生器。 第一相量发生器基于要通过数据总线发送的数据获得第一数据值，并生成第一相量。 第二相量发生器基于要通过数据总线发送的数据获得第二数据值，并生成第二相量。 第一相量和第二相量的总和至少部分地表示要通过数据总线发送的数据的频谱内容。