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1.发明公开公开(公告)号：US20240234227A9
公开(公告)日：2024-07-11
申请号：US18485953
申请日：2023-10-12
Applicant: Infineon Technologies AG
Inventor： Martin MAYER , Rainer Markus SCHALLER
CPC classification number: H01L23/295 , H01L21/565 , H01L23/3107 , H01L24/48 , H01L2224/48245 , H01L2924/186
Abstract: A semiconductor device contains a chip carrier and a semiconductor chip arranged on the chip carrier. Furthermore, the semiconductor device comprises an intermediate layer arranged between the chip carrier and the semiconductor chip, and an encapsulation material at least partially encapsulating the semiconductor chip. Filler particles are embedded in at least one of the interlayer or the encapsulation material, wherein the filler particles contain a semiconductor material with a band gap in a range from 2.3 eV to 3.6 eV.
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2.发明公开
公开(公告)号：US20240153885A1
公开(公告)日：2024-05-09
申请号：US18498537
申请日：2023-10-31
Applicant: Infineon Technologies AG
Inventor： Rainer Markus SCHALLER , Martin MAYER , Volker STRUTZ
IPC: H01L23/552 , G01R15/20 , G01R19/00 , H01L21/48 , H01L23/00 , H01L23/495
CPC classification number: H01L23/552 , G01R15/202 , G01R19/0092 , H01L21/4803 , H01L21/4846 , H01L23/49534 , H01L23/49589 , H01L24/48 , H01L2224/48091 , H01L2224/48245
Abstract: A semiconductor device contains an electrically conductive carrier and a semiconductor chip arranged on the carrier. Furthermore, the semiconductor device contains a layer stack arranged between the carrier and the semiconductor chip and having a plurality of dielectric layers. The layer stack galvanically isolates the semiconductor chip and the carrier from one another. At least one of the plurality of dielectric layers is coated with an electrically conductive coating.
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3.发明申请
公开(公告)号：US20230064442A1
公开(公告)日：2023-03-02
申请号：US17879900
申请日：2022-08-03
Applicant: Infineon Technologies AG
Inventor： Chan Whai Augustine KAN , Martin MAYER , Edmund RIEDL , Edward FUERGUT , Harry Walter SAX
IPC: H01L23/367 , H01L23/31 , H01L23/42 , H01L23/00
Abstract: A chip package structure is disclosed. In one example, the chip package may include a chip, an encapsulation material, and an exposed pad that is electrically conductively connected to the chip. A layer of a porous or dendrite-comprising adhesion promoter is on a surface of the exposed pad. A thermal interface material that is attached to the exposed pad by the layer.
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公开(公告)号：US20210166986A1
公开(公告)日：2021-06-03
申请号：US17101387
申请日：2020-11-23
Applicant: Infineon Technologies AG
Inventor： Alexander ROTH , Stefan SCHWAB , Martin MAYER
Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, an encapsulant encapsulating at least part of the carrier and at least part of the electronic component. A compression structure is provided that applies compressive stress to at least part of the encapsulant.
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公开(公告)号：US20240030092A1
公开(公告)日：2024-01-25
申请号：US18351284
申请日：2023-07-12
Applicant: Infineon Technologies AG
Inventor： Tuncay ERDOEL , Walter HARTNER , Pietro BRENNER , Simon KORNPROBST , Martin MAYER
IPC: H01L23/373 , H01L23/552 , H01L23/31
CPC classification number: H01L23/373 , H01L23/552 , H01L23/3107
Abstract: A device includes a radio frequency chip and a heat sink arranged over the radio frequency chip. The device further includes a layer stack arranged between the radio frequency chip and the heat sink. The layer stack includes a first layer including a first material, a thermal interface material, and a metal layer arranged between the first material and the thermal interface material.
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6.发明公开
公开(公告)号：US20240136240A1
公开(公告)日：2024-04-25
申请号：US18485953
申请日：2023-10-11
Applicant: Infineon Technologies AG
Inventor： Martin MAYER , Rainer Markus SCHALLER
CPC classification number: H01L23/295 , H01L21/565 , H01L23/3107 , H01L24/48 , H01L2224/48245 , H01L2924/186
Abstract: A semiconductor device contains a chip carrier and a semiconductor chip arranged on the chip carrier. Furthermore, the semiconductor device comprises an intermediate layer arranged between the chip carrier and the semiconductor chip, and an encapsulation material at least partially encapsulating the semiconductor chip. Filler particles are embedded in at least one of the interlayer or the encapsulation material, wherein the filler particles contain a semiconductor material with a band gap in a range from 2.3 eV to 3.6 eV.
