公开(公告)号：US5336941A

公开(公告)日：1994-08-09

申请号：US925019

申请日：1992-08-05

Applicant: Ichiro Ishida

Inventor： Ichiro Ishida

IPC: H01L39/22 ,  H03K3/38 ,  H03K19/195

CPC classification number: H03K19/1956 ,  H03K3/38 ,  Y10S505/864

Abstract: According to the present invention, there is provided a superconducting circuit including a Josephson tunnel junction 1 and a load resistor 2 connected in parallel to the Josephson tunnel junction, in which a current source 5 is connected to the input terminal for the Josephson tunnel junction 1 and which has a pulse generator 3 in order to superimpose a pulse current to the current i from the current source 5.As the input signal, a current pulse is given to the current i within the range of below the critical current of the Josephson tunnel junction by means of the foregoing pulse generator 3 so that an excellent separation of the input and output is achieved without using any magnetic coupling circuit.

Abstract translation: 根据本发明，提供了一种超导电路，其包括并联连接到约瑟夫逊隧道结的约瑟夫逊隧道结1和负载电阻器2，其中电流源5连接到约瑟夫逊隧道结1的输入端 并且其具有脉冲发生器3，以便从电流源5向电流i叠加脉冲电流。作为输入信号，在低于约瑟夫森隧道的临界电流的范围内给电流i施加电流脉冲 通过上述脉冲发生器3连接，从而在不使用任何磁耦合电路的情况下实现输入和输出的良好分离。

公开(公告)号：US4601015A

公开(公告)日：1986-07-15

申请号：US467631

申请日：1983-02-18

Applicant: Ichiro Ishida

Inventor： Ichiro Ishida

IPC: G11C11/44

CPC classification number: G11C11/44 ,  Y10S505/832

Abstract: A Josephson memory circuit comprises a closed superconducting loop having a first node and including a first Josephson gate therein, and a first line connected to the node. The circuit also includes a second line provided to electromagnetically couple to the first Josephson gate, a second Josephson gate provided so close to the superconducting loop as to electromagnetically couple to the superconducting loop, and a third line connected to the second Josephson gate and provided to electromagnetically couple to the first Josephson gate.

Abstract translation: 约瑟夫森存储器电路包括具有第一节点并且在其中包括第一约瑟夫逊门的闭合超导环路和连接到该节点的第一线路。 电路还包括提供用于电磁耦合到第一约瑟夫森门的第二线，第二约瑟夫逊门，其设置为与超导环相近，以电磁耦合到超导回路，以及连接到第二约瑟夫森门的第三线， 电磁耦合到第一个约瑟夫森门。

公开(公告)号：US07112446B2

公开(公告)日：2006-09-26

申请号：US10097010

申请日：2002-03-14

Applicant: Hirotaka Minagawa ,  Ichiro Ishida ,  Akira Tsugita ,  Takuji Nabetani

Inventor： Hirotaka Minagawa ,  Ichiro Ishida ,  Akira Tsugita ,  Takuji Nabetani

IPC: G01N33/00

CPC classification number: G01N33/6842 ,  G01N33/6803 ,  Y10T436/15 ,  Y10T436/153333 ,  Y10T436/24

Abstract: In a method for efficiently analyzing a posttranslational modification of a protein using no enzyme, a protein or peptide to be analyzed is reacted with an acid (a thioester or hydrazine) under certain conditions. This makes it possible to detect variously modified states of a protein or peptide, whereby the identification of each specific modifying group and the position of each modified amino acid can be efficiently analyzed using a chemical method and a mass spectrometric apparatus.

Abstract translation: 在不使用酶有效分析蛋白质的翻译后修饰的方法中，将待分析的蛋白质或肽在某些条件下与酸（硫酯或肼）反应。 这使得可以检测蛋白质或肽的各种修饰的状态，从而可以使用化学方法和质谱仪有效地分析每个特定修饰基团的鉴定和每个修饰的氨基酸的位置。

公开(公告)号：US5326988A

公开(公告)日：1994-07-05

申请号：US999656

申请日：1992-12-29

Applicant: Ichiro Ishida

Inventor： Ichiro Ishida

IPC: H01L39/22 ,  H01L39/14 ,  H01L39/24 ,  H01L27/12 ,  H01L45/00

CPC classification number: H01L39/146

Abstract: A superconducting device including first and second trenches formed on a principal surface of a semiconductor substrate, separated from each other, and first and second superconductor electrodes filled in the first and second trenches and planarized to have a surface coplanar with the principal surface of the semiconductor substrate. The first and second superconductor electrodes form a separation zone which is defined by opposing sides of the first and second superconductor electrodes. An insulating layer is formed to cover a portion of the first superconductor electrode, the separation zone and a portion of the second superconductor electrode, and a gate electrode is formed on the insulating layer so as to be positioned above at least the separation zone. The above mentioned superconducting device can be formed by forming first and second trenches on a principal surface of a semiconductor substrate separate from each other, and depositing a superconductor layer so as to cover a whole of the principal surface of the semiconductor substrate. A resin layer is deposited on the whole of the principal surface of the semiconductor substrate, and etch-back is performed to completely remove the deposited resin layer and also to remove the deposited superconductor layer from a surface excluding the first and second trenches, so that the superconductor layer remaining in the first and second trenches respectively form first and second superconductor electrodes planarized to have a surface coplanar with the principal surface of the semiconductor substrate. An insulating layer and a gate electrode are formed to cover at least a separation zone between the first and second trenches.

Abstract translation: 一种超导装置，包括形成在半导体衬底的主表面上的彼此分离的第一和第二沟槽以及填充在第一和第二沟槽中的第一和第二超导体电极，并且被平坦化以具有与半导体的主表面共面的表面 基质。 第一和第二超导体电极形成由第一和第二超导体电极的相对侧限定的分离区。 形成绝缘层以覆盖第一超导体电极的一部分，分离区和第二超导体电极的一部分，并且在绝缘层上形成栅电极以至少位于至少分离区之上。 上述超导装置可以通过在半导体基板的彼此分离的主表面上形成第一和第二沟槽，并且沉积超导体层以覆盖半导体衬底的整个主表面而形成。 树脂层沉积在半导体衬底的整个主表面上，并且进行回蚀以完全去除沉积的树脂层，并且还从除第一和第二沟槽之外的表面去除沉积的超导体层，使得 残留在第一和第二沟槽中的超导体层分别形成平面化以具有与半导体衬底的主表面共面的表面的第一和第二超导体电极。 形成绝缘层和栅电极以至少覆盖第一和第二沟槽之间的分隔区。

公开(公告)号：US5304817A

公开(公告)日：1994-04-19

申请号：US886949

申请日：1992-05-22

Applicant: Ichiro Ishida

Inventor： Ichiro Ishida

IPC: H01L39/22 ,  H01L39/24

CPC classification number: H01L39/2496 ,  H01L39/225

Abstract: A superconductive circuit is fabricated on a substrate with a major surface, and comprises a wiring layer of superconductive oxide with the a-b plane orientation substantially parallel to the major surface, and a Josephson junction electrically coupled with the wiring layer, wherein the josephson junction comprises a lower electrode of superconductive oxide having the a-b plane orientation substantially perpendicular to the major surface and embedded into the wiring layer so that the structure achieves both long coherent length desirable for large design margin of the junction as well as large amount of current passing through the wiring layer.

Abstract translation: 在具有主表面的基板上制造超导电路，并且包括具有基本上平行于主表面的ab平面取向的超导氧化物的布线层以及与布线层电耦合的约瑟夫逊结，其中约瑟夫森结包括 具有ab面取向基本上垂直于主表面并且嵌入到布线层中的超导氧化物的下电极，使得该结构实现了对于结的大的设计边缘以及大量电流通过布线所需的长相干长度 层。