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    TRANSISTORS WITH SOURCE & DRAIN ETCH STOP
    2.
    发明申请
    TRANSISTORS WITH SOURCE & DRAIN ETCH STOP 有权

    公开(公告)号：US20220415708A1

    公开(公告)日：2022-12-29

    申请号：US17358903

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Stephen Cea ,  Tahir Ghani ,  Patrick Keys ,  Aaron Lilak ,  Anand Murthy ,  Cory Weber

    IPC: H01L21/768 ,  H01L29/10 ,  H01L27/088 ,  H01L25/07 ,  H01L29/66 ,  H01L29/78

    Abstract: Integrated circuitry comprising transistor structures with a source/drain etch stop layer to limit the depth of source and drain material relative to a channel of the transistor. A portion of a channel material layer may be etched in preparation for source and drain materials. The etch may be stopped at an etch stop layer buried between a channel material layer and an underlying planar substrate layer. The etch stop layer may have a different composition than the channel layer while retaining crystallinity of the channel layer. The source and drain etch stop layer may provide adequate etch selectivity to ensure a source and drain etch process does not punch through the etch stop layer. Following the etch process, source and drain materials may be formed, for example with an epitaxial growth process. The source and drain etch stop layer may be, for example, primarily silicon and carbon.

    Wrap-around contact structures for semiconductor nanowires and nanoribbons
    3.
    发明授权
    Wrap-around contact structures for semiconductor nanowires and nanoribbons 有权

    公开(公告)号：US11527640B2

    公开(公告)日：2022-12-13

    申请号：US16238978

    申请日：2019-01-03

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea ,  Biswajeet Guha

    IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

    Channel structures with sub-fin dopant diffusion blocking layers
    5.
    发明授权
    Channel structures with sub-fin dopant diffusion blocking layers 有权

    公开(公告)号：US11521968B2

    公开(公告)日：2022-12-06

    申请号：US16024671

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

    IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/092

    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

    Wrap-around contact structures for semiconductor nanowires and nanoribbons
    7.
    发明授权
    Wrap-around contact structures for semiconductor nanowires and nanoribbons 有权

    公开(公告)号：US12176429B2

    公开(公告)日：2024-12-24

    申请号：US18379548

    申请日：2023-10-12

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea ,  Biswajeet Guha

    IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

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