-
公开(公告)号：US11294749B2
公开(公告)日：2022-04-05
申请号：US15859474
申请日：2017-12-30
Applicant: Intel Corporation
Inventor： Ramamurthy Krithivas , Anand K. Enamandram , Eswaramoorthi Nallusamy , Russell J. Wunderlich , Krishnakanth V. Sistla
IPC: G06F11/07
Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.
-
公开(公告)号：US10331614B2
公开(公告)日：2019-06-25
申请号：US15025988
申请日：2013-11-27
Applicant: INTEL CORPORATION , Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
Inventor： Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
-
3.发明申请METHOD AND APPARATUS FOR SERVER PLATFORM ARCHITECTURES THAT ENABLE SERVICEABLE NONVOLATILE MEMORY MODULES 审中-公开使用可维修非易失性存储器模块的服务器平台架构的方法和设备公开(公告)号：US20160239460A1
公开(公告)日：2016-08-18
申请号：US15025988
申请日：2013-11-27
Applicant: INTEL CORPORATION
Inventor： Dimitrios Ziakas , Bassam N. Coury , Mohan J. Kumar , Murugasamy K. Nachimuthu , Thi Dang , Russell J. Wunderlich
CPC classification number: G06F15/7803 , G06F11/1068 , G06F11/108 , G06F11/1092 , G06F11/1662 , G06F11/3485 , G06F2201/805
Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.
Abstract translation: 实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。 这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。 相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。 该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入端可通信地耦合到布置在前端或后端装载机架中的至少一些NVM /存储模块 /输出（I / O）通道。 通过采用可以在计算机系统的前端或后端加载接收的NVM /存储模块，系统和方法提供了存储器组件在实现常规服务器架构的计算机系统中无法实现的可维护性。
-
Patent Agency Ranking
公开(公告)号：US10929330B2
公开(公告)日：2021-02-23
申请号：US15639035
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Chih-Cheh Chen , Russell J. Wunderlich , Tina C. Zhong
IPC: G06F13/40
Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.
-
公开(公告)号：US09502082B1
公开(公告)日：2016-11-22
申请号：US14748728
申请日：2015-06-24
Applicant: Intel Corporation
Inventor： Thi Dang , James S. Burns , Russell J. Wunderlich , Jagannath Coimbatore Premkumar
CPC classification number: G11C5/147 , G06F1/26 , G06F1/3225 , G06F1/3275 , G06F1/3296 , G11C5/14 , G11C11/005 , G11C11/2297 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch, connected to an output of the sensor, controls power to the non-volatile RAM, and a voltage regulator regulates a voltage of the non-volatile RAM and the volatile RAM. One or more memory slots receive the non-volatile RAM and the volatile RAM, and a processor receives information from the sensor, and controls the voltage regulator based on the received information. The voltage regulator comprises a plurality of registers to store power consumption information of the non-volatile RAM and the volatile RAM.
Abstract translation: 方法，设备和系统可以提供传感器以监视非易失性随机存取存储器（RAM）和易失性RAM的功耗。 连接到传感器输出的开关控制非易失性RAM的电源，电压调节器调节非易失性RAM和易失性RAM的电压。 一个或多个存储器插槽接收非易失性RAM和易失性RAM，并且处理器从传感器接收信息，并且基于接收到的信息来控制电压调节器。 电压调节器包括多个寄存器以存储非易失性RAM和易失性RAM的功耗信息。
-
公开(公告)号：US20210183846A1
公开(公告)日：2021-06-17
申请号：US17185504
申请日：2021-02-25
Applicant: Intel Corporation
Inventor： Jeffory L. Smalley , Thomas Holden , Russell J. Wunderlich , Farzaneh Yahyaei-Moayyed , Mohanraj Prabhugoud , Horthense Delphine Tamdem , Vijaya Boddu , Kaladhar Radhakrishnan , Timothy Glen Hanna , Krishna Bharath , Judy Amanor-Boadu , Mark A. Schmisseur , Srikant Nekkanty , Luis E. Rosales Galvan
IPC: H01L25/18 , H01L23/498 , H01R12/71
Abstract: A processor module comprises an integrated circuit component attached to a power interposer. One or more voltage regulator modules attach to the power interposer via interconnect sockets and the power interposer routes regulated power signals generated by the voltage regulator modules to the integrated circuit component. Input power signals are provided to the voltage regulator from the system board via straight pins, a cable connector, or another type of connector. The integrated circuit component's I/O signals are routed through the power interposer to a system board via a socket located between the power interposer and the socket. Not having to route regulated power signals from a system board through a socket to an integrated circuit component can result in a system board with fewer layers, which can reduce overall system cost, as well as creating more area available in the remaining layers for I/O signal entry to the socket.
-
公开(公告)号：US20190095224A1
公开(公告)日：2019-03-28
申请号：US15719340
申请日：2017-09-28
Applicant: Intel Corporation
Inventor： Tina C. Zhong , Russell J. Wunderlich , Chih-Cheh Chen , Malay Trivedi
Abstract: Embodiments disclosed herein relate to coordinated system boot and reset flows and improve reliability, availability, and serviceability (RAS) among multiple chipsets. In an example, a system includes a master chipset having multiple interfaces, each interface to connect to one of a processor and a chipset, at least one processor connected to the master chipset, at least one non-master chipset connected to the master chipset, and a sideband messaging channel connecting the master chipset and the non-master chipsets, wherein the master chipset is to probe a subset of its multiple interfaces to discover a topology of connected processors and non-master chipsets, and use the sideband messaging channel to coordinate a synchronized boot flow.
-
公开(公告)号：US20190004989A1
公开(公告)日：2019-01-03
申请号：US15639035
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Chih-Cheh Chen , Russell J. Wunderlich , Tina C. Zhong
IPC: G06F13/40
Abstract: Examples may include chipsets, processor circuits, and a system including chipsets and processor circuits. The chipsets and processor circuits can be coupled together via side band interconnect. The chipsets and processor circuits can be coupled together dynamically, during runtime using the side band interconnects. A chipset can send control signals for other chipsets and/or receive control signals from processor circuits via the side band links to dynamically coordinate the chipsets and processor circuits into systems.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.013 seconds)
