公开(公告)号：US09832876B2

公开(公告)日：2017-11-28

申请号：US14575775

申请日：2014-12-18

Applicant: INTEL CORPORATION

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US20170264055A1

公开(公告)日：2017-09-14

申请号：US15607327

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Yunhui Chu ,  Charles C. Phares ,  John M. Lynch

IPC: H01R13/703 ,  H01R13/24

CPC classification number: H01R13/7035 ,  G06F13/4086 ,  H01R12/7094 ,  H01R13/24 ,  H01R13/2435 ,  H01R13/6473 ,  H01R13/7034

Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.

公开(公告)号：US20170187151A1

公开(公告)日：2017-06-29

申请号：US14757951

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yunhui Chu ,  Charles C. Phares ,  John M. Lynch

IPC: H01R13/703 ,  H01R13/24

CPC classification number: H01R13/7035 ,  G06F13/4086 ,  H01R12/7094 ,  H01R13/24 ,  H01R13/2435 ,  H01R13/6473 ,  H01R13/7034

Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.

公开(公告)号：US09941643B2

公开(公告)日：2018-04-10

申请号：US14757951

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Yunhui Chu ,  Charles C. Phares ,  John M. Lynch

IPC: H01R29/00 ,  H01R13/703 ,  H01R13/24

CPC classification number: H01R13/7035 ,  G06F13/4086 ,  H01R12/7094 ,  H01R13/24 ,  H01R13/2435 ,  H01R13/6473 ,  H01R13/7034

Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.

公开(公告)号：US09935384B1

公开(公告)日：2018-04-03

申请号：US15280281

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  John M. Lynch

IPC: H01R13/62 ,  H01R12/70 ,  H01R13/633 ,  H01R12/73 ,  H01R43/20

CPC classification number: H01R12/7058 ,  H01R12/721 ,  H01R12/737 ,  H01R13/6335 ,  H01R43/205 ,  H05K7/1409

Abstract: A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.

公开(公告)号：US20170271818A1

公开(公告)日：2017-09-21

申请号：US15074094

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： John M. Lynch ,  Chong Richard Zhao ,  Xiang Li ,  Donald T. Tran

IPC: H01R13/6461 ,  H01R12/75 ,  H01R12/73

CPC classification number: H01R13/6461 ,  H01R12/72 ,  H01R12/721 ,  H01R12/73 ,  H01R12/737 ,  H01R12/75 ,  H01R13/658 ,  H01R13/6585 ,  H01R13/6586 ,  H01R23/6873

Abstract: An example electronic assembly for securing an electronic card. In some forms, the electronic assembly further includes a printed circuit board. The electronic assembly includes a housing having a first set of electrical contacts and a second set of electrical contacts. The housing is configured to receive the electronic card between the first and second set of electrical contacts. The housing further includes a third set of electrical contacts and a fourth set of electrical contacts. The housing is configured to receive the electronic card between the third and fourth set of electrical contacts. A ground shield is positioned between at least one of the first and third set of electrical contacts and the second and fourth set of electrical contacts. In some forms, the ground shield may be positioned between both the first and third set of electrical contacts and the second and fourth set of electrical contacts.

公开(公告)号：US09929511B2

公开(公告)日：2018-03-27

申请号：US15074094

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： John M. Lynch ,  Chong Richard Zhao ,  Xiang Li ,  Donald T. Tran

IPC: H01R12/72 ,  H01R13/6461 ,  H01R12/73 ,  H01R12/75 ,  H01R13/658 ,  H01R13/6586 ,  H01R12/50 ,  H01R13/6585

CPC classification number: H01R13/6461 ,  H01R12/72 ,  H01R12/721 ,  H01R12/73 ,  H01R12/737 ,  H01R12/75 ,  H01R13/658 ,  H01R13/6585 ,  H01R13/6586 ,  H01R23/6873

Abstract: An example electronic assembly for securing an electronic card. In some forms, the electronic assembly further includes a printed circuit board. The electronic assembly includes a housing having a first set of electrical contacts and a second set of electrical contacts. The housing is configured to receive the electronic card between the first and second set of electrical contacts. The housing further includes a third set of electrical contacts and a fourth set of electrical contacts. The housing is configured to receive the electronic card between the third and fourth set of electrical contacts. A ground shield is positioned between at least one of the first and third set of electrical contacts and the second and fourth set of electrical contacts. In some forms, the ground shield may be positioned between both the first and third set of electrical contacts and the second and fourth set of electrical contacts.

公开(公告)号：US20180007791A1

公开(公告)日：2018-01-04

申请号：US15702709

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/498 ,  H01R12/71 ,  H01R12/79

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

公开(公告)号：US10426381B2

公开(公告)日：2019-10-01

申请号：US15607333

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Yunhui Chu ,  Charles C. Phares ,  John M. Lynch

IPC: H01R29/00 ,  A61B5/117 ,  G06F21/32 ,  G06K9/00 ,  G06F21/83

Abstract: Switchable grounded terminal loads are built into, or otherwise coupled to, connectors on motherboards and control devices. The terminal loads are coupled to the bus termination at the connector when the connector is “stuffed” (connected to a mating connector). The switchable grounded terminal loads replace dummy connectors in preventing empty “unstuffed” connectors from increasing error risks on active channels.

公开(公告)号：US20180090862A1

公开(公告)日：2018-03-29

申请号：US15280281

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Xiang Li ,  George Vergis ,  John M. Lynch

IPC: H01R12/70 ,  H01R13/633 ,  H01R12/73 ,  H01R43/20

CPC classification number: H01R12/7058 ,  H01R12/721 ,  H01R12/737 ,  H01R13/6335 ,  H01R43/205 ,  H05K7/1409

Abstract: A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.