公开(公告)号：US20190138305A1

公开(公告)日：2019-05-09

申请号：US16003555

申请日：2018-06-08

Applicant: INTEL CORPORATION

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

公开(公告)号：US12086080B2

公开(公告)日：2024-09-10

申请号：US17033728

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： George Chrysos ,  Bhargavi Narayanasetty ,  Jesus Corbal ,  Ching-Kai Liang ,  Chinmay Ashok ,  Francis Tseng

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/4027

Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.

公开(公告)号：US09996347B2

公开(公告)日：2018-06-12

申请号：US14582784

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

公开(公告)号：US20160188334A1

公开(公告)日：2016-06-30

申请号：US14582784

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

CPC classification number: G06F9/30036

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.

Abstract translation: 描述与具有具有基本偏移的寄存器操作数的向量指令相关的方法和装置。 在一个实施例中，硬件处理器包括解码单元，用于对具有基本偏移量的寄存器操作数解码向量指令，以访问由寄存器操作数指定的寄存器中的第一数量的元素，其中第一个数字是元素的总数 在所述寄存器中减去所述元素偏移量，访问下一逻辑寄存器中的第二数量的元素，其中所述第二数量是所述元素偏移量，并且将所述第一数量的元素和所述第二数量的元素组合为数据向量，以及执行 单元来执行数据向量的向量指令。

公开(公告)号：US10719317B2

公开(公告)日：2020-07-21

申请号：US16003555

申请日：2018-06-08

Applicant: INTEL CORPORATION

Inventor： Victor Lee ,  Ugonna Echeruo ,  George Chrysos ,  Naveen Mellempudi

IPC: G06F9/30

Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.