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公开(公告)号：US10211120B2
公开(公告)日：2019-02-19
申请号：US14998123
申请日：2015-12-23
Applicant: Intel Corporation
Inventor： Russell S. Aoki , Jonathan W. Thibado , Jeffory L. Smalley , David J. Llapitan , Thomas A. Boyd , Harvey R. Kofstad , Dimitrios Ziakas , Hongfei Yan
IPC: H01L23/34 , H01L23/498 , H05K1/02 , H05K1/14 , H05K3/34
Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.
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公开(公告)号：US09832876B2
公开(公告)日：2017-11-28
申请号：US14575775
申请日：2014-12-18
Applicant: INTEL CORPORATION
Inventor： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
CPC classification number: H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
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公开(公告)号：US09490560B2
公开(公告)日：2016-11-08
申请号：US14576735
申请日：2014-12-19
Applicant: INTEL CORPORATION
Inventor： Gaurav Chawla , David J. Llapitan , Jeffory L. Smalley , Tejinder Pal Aulakh , Vijaykumar Krithivasan , Donald T. Tran
CPC classification number: H01R12/79 , G06F1/18 , H01R43/205 , H05K7/1069 , H05K7/1092
Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
Abstract translation: 描述了使用弹簧偏压的多阵列底侧阵列的连接器。 在一个示例中，连接器包括连接器壳体，连接器壳体具有底表面，以及与底表面相对的多个弹性连接器，以电连接到集成电路封装的对应的多个焊盘;电缆连接器，用于电连接 电缆的弹性连接器，具有压靠电路板的底表面的基板和与底表面相对的顶表面，以及联接在基板和连接器底表面之间的多个弹簧构件，用于将基板 底部表面靠在系统板上，并将连接器外壳连接件按压在包装上。
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公开(公告)号：US20160181714A1
公开(公告)日：2016-06-23
申请号：US14576735
申请日：2014-12-19
Applicant: INTEL CORPORATION
Inventor： GAURAV CHAWLA , David J. Llapitan , Jeffory L. Smalley , Tejinder Pal Aulakh , Vijaykumar Krithivasan , Donald T. Tran
CPC classification number: H01R12/79 , G06F1/18 , H01R43/205 , H05K7/1069 , H05K7/1092
Abstract: A connector for a multi-array bottom side array is described that uses a spring bias. In one example, a connector includes a connector housing, the connector housing having a bottom surface, and a plurality of resilient connectors opposite the bottom surface to electrically connect to a corresponding plurality of pads of an integrated circuit package, a cable connector to electrically connect the resilient connectors to a cable, a base plate having a bottom surface to press against a circuit board, and a top surface opposite the bottom surface, and plurality of spring members coupled between the base plate and the connector bottom surface to press the base plate bottom surface against the system board and to press the connector housing connectors against the package.
Abstract translation: 描述了使用弹簧偏压的多阵列底侧阵列的连接器。 在一个示例中，连接器包括连接器壳体，连接器壳体具有底表面，以及与底表面相对的多个弹性连接器，以电连接到集成电路封装的对应的多个焊盘;电缆连接器，用于电连接 电缆的弹性连接器，具有压靠电路板的底表面的基板和与底表面相对的顶表面，以及联接在基板和连接器底表面之间的多个弹簧构件，用于将基板 底部表面靠在系统板上，并将连接器外壳连接件按压在包装上。
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公开(公告)号：US20150249298A1
公开(公告)日：2015-09-03
申请号：US14563641
申请日：2014-12-08
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Joshua D. Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
CPC classification number: H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的示例包括具有两个或更多台阶的插头和插座，其具有沿着梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。
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公开(公告)号：US20180007791A1
公开(公告)日：2018-01-04
申请号：US15702709
申请日：2017-09-12
Applicant: Intel Corporation
Inventor： Mani Prakash , Thomas T. Holden , Jeffory L. Smalley , Ram S. Viswanath , Bassam N. Coury , Dimitrios Ziakas , Chong J. Zhao , Jonathan W. Thibado , Gregorio R. Murtagian , Kuang C. Liu , Rajasekaran Swaminathan , Zhichao Zhang , John M. Lynch , David J. Llapitan , Sanka Ganesan , Xiang Li , George Vergis
IPC: H05K1/18 , H01L23/00 , H01L23/498 , H01R12/71 , H01R12/79
CPC classification number: H05K1/181 , H01L23/00 , H01L23/498 , H01L2224/16225 , H01L2924/15311 , H01R12/712 , H01R12/79 , H05K2201/10159 , H05K2201/10325 , Y02P70/611
Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
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公开(公告)号：US20160183375A1
公开(公告)日：2016-06-23
申请号：US14578037
申请日：2014-12-19
Applicant: Intel Corporation
Inventor： Vijaykumar Krithivasan , Jeffory L. Smalley , David J. Llapitan , Gaurav Chawla , Mani Prakash , Susan F. Smith
IPC: H05K1/18 , H01L23/40 , H01L23/498 , B23P15/26 , H01L21/48 , H05K3/32 , H05K7/20 , H01L23/367 , H01L21/50
CPC classification number: H05K7/2039 , H01L23/32 , H01L23/36 , H01L23/40 , H01L2924/0002 , H05K2201/10378 , H05K2201/1056 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
Abstract translation: 本公开的实施例针对套接字加载元件和相关联的技术和配置。 在一个实施例中，设备可以包括加载元件，该加载元件被配置为将压缩负载从散热器传送到插座组件，其中所述加载元件构造成当所述加载元件与设置在 模具和插座组件，并且其中装载元件包括构造成容纳模具的开口。 可以描述和/或要求保护其他实施例。
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公开(公告)号：US09385457B2
公开(公告)日：2016-07-05
申请号：US14563641
申请日：2014-12-08
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Joshua D Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
CPC classification number: H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。
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公开(公告)号：US08905794B2
公开(公告)日：2014-12-09
申请号：US13711187
申请日：2012-12-11
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Joshua D Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
CPC classification number: H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。
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公开(公告)号：US09848510B2
公开(公告)日：2017-12-19
申请号：US14578037
申请日：2014-12-19
Applicant: Intel Corporation
Inventor： Vijaykumar Krithivasan , Jeffory L. Smalley , David J. Llapitan , Gaurav Chawla , Mani Prakash , Susan F. Smith
CPC classification number: H05K7/2039 , H01L23/32 , H01L23/36 , H01L23/40 , H01L2924/0002 , H05K2201/10378 , H05K2201/1056 , H01L2924/00
Abstract: Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an apparatus may include a loading element configured to transfer a compressive load from a heat spreader to a socket assembly, wherein the loading element is configured to form a perimeter around a die when the loading element is coupled with an interposer disposed between the die and the socket assembly and wherein the loading element includes an opening configured to accommodate the die. Other embodiments may be described and/or claimed.
