公开(公告)号：US11916059B2

公开(公告)日：2024-02-27

申请号：US17411060

申请日：2021-08-25

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

IPC: H01L23/60 ,  H01L27/02 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

CPC classification number: H01L27/0248 ,  H01L21/78 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/60 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H02H9/04 ,  H01L27/0744 ,  H01L29/74 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/30205 ,  H01L2924/1301 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

公开(公告)号：US10672758B2

公开(公告)日：2020-06-02

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/87 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

公开(公告)号：US20150194480A1

公开(公告)日：2015-07-09

申请号：US14665521

申请日：2015-03-23

Applicant: Infineon Technologies AG

Inventor： Wolfgang Lehnert ,  Stefan Pompl ,  Markus Meyer

IPC: H01L29/04 ,  H01L29/16 ,  H01L29/94

CPC classification number: H01L29/04 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/763 ,  H01L21/823828 ,  H01L28/60 ,  H01L29/16 ,  H01L29/51 ,  H01L29/7833 ,  H01L29/945

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract translation: 公开了一种形成压缩多晶半导体材料层的方法。 该方法包括在衬底上形成多晶半导体种子层并通过在低于600℃的温度的无定形工艺条件下将硅直接沉积在多晶硅籽晶层上形成硅层。

公开(公告)号：US09583559B2

公开(公告)日：2017-02-28

申请号：US14665521

申请日：2015-03-23

Applicant: Infineon Technologies AG

Inventor： Wolfgang Lehnert ,  Stefan Pompl ,  Markus Meyer

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/763 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/16 ,  H01L29/51 ,  H01L29/78 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L29/04 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/763 ,  H01L21/823828 ,  H01L28/60 ,  H01L29/16 ,  H01L29/51 ,  H01L29/7833 ,  H01L29/945

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract translation: 公开了一种形成压缩多晶半导体材料层的方法。 该方法包括在衬底上形成多晶半导体种子层并通过在低于600℃的温度的无定形工艺条件下将硅直接沉积在多晶硅籽晶层上形成硅层。

公开(公告)号：US09196675B2

公开(公告)日：2015-11-24

申请号：US14170085

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Wolfgang Lehnert ,  Michael Stadtmueller ,  Stefan Pompl ,  Markus Meyer

IPC: H01L27/108 ,  H01L29/66 ,  H01L29/94 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.

Abstract translation: 公开了半导体器件和半导体器件的制造方法。 该方法包括在衬底中形成沟槽，用第一半导体材料部分地填充沟槽，沿着第一半导体材料的表面形成界面，并用第二半导体材料填充沟槽。 半导体器件包括沿着沟槽的侧壁布置的第一电极和布置在第一电极上的电介质。 所述半导体器件还包括至少部分地填充所述沟槽的第二电极，其中所述第二电极包括所述第二电极内的界面。

公开(公告)号：US20140145305A1

公开(公告)日：2014-05-29

申请号：US14170085

申请日：2014-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Wolfgang Lehnert ,  Michael Stadtmueller ,  Stefan Pompl ,  Markus Meyer

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.

Abstract translation: 公开了半导体器件和半导体器件的制造方法。 该方法包括在衬底中形成沟槽，用第一半导体材料部分地填充沟槽，沿着第一半导体材料的表面形成界面，并用第二半导电材料填充沟槽。 半导体器件包括沿着沟槽的侧壁布置的第一电极和布置在第一电极上的电介质。 所述半导体器件还包括至少部分地填充所述沟槽的第二电极，其中所述第二电极包括所述第二电极内的界面。

公开(公告)号：US20180108648A1

公开(公告)日：2018-04-19

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

公开(公告)号：US20160043164A1

公开(公告)日：2016-02-11

申请号：US14918190

申请日：2015-10-20

Applicant: Infineon Technologies AG

Inventor： Wolfgang Lehnert ,  Michael Stadtmueller ,  Stefan Pompl ,  Markus Meyer

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L27/10829 ,  H01L27/10861 ,  H01L29/66181 ,  H01L29/945

Abstract: A method for manufacturing a semiconductor device and a semiconductor device are disclosed. The method comprises forming a trench in a substrate, partially filling the trench with a first semiconductive material, forming an interface along a surface of the first semiconductive material, and filling the trench with a second semiconductive material. The semiconductor device includes a first electrode arranged along sidewalls of a trench and a dielectric arranged over the first electrode. The semiconductor device further includes a second electrode at least partially filling the trench, wherein the second electrode comprises an interface within the second electrode.

Abstract translation: 公开了半导体器件和半导体器件的制造方法。 该方法包括在衬底中形成沟槽，用第一半导体材料部分地填充沟槽，沿着第一半导体材料的表面形成界面，并用第二半导体材料填充沟槽。 半导体器件包括沿着沟槽的侧壁布置的第一电极和布置在第一电极上的电介质。 所述半导体器件还包括至少部分地填充所述沟槽的第二电极，其中所述第二电极包括所述第二电极内的界面。

公开(公告)号：US09012295B2

公开(公告)日：2015-04-21

申请号：US13660966

申请日：2012-10-25

Applicant: Infineon Technologies AG

Inventor： Wolfgang Lehnert ,  Stefan Pompl ,  Markus Meyer

IPC: H01L21/20 ,  H01L21/00 ,  H01L21/36 ,  H01L29/94 ,  H01L21/02 ,  H01L49/02 ,  H01L21/28 ,  H01L21/763 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/04 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/763 ,  H01L21/823828 ,  H01L28/60 ,  H01L29/16 ,  H01L29/51 ,  H01L29/7833 ,  H01L29/945

Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.

Abstract translation: 公开了一种形成压缩多晶半导体材料层的方法。 该方法包括在衬底上形成多晶半导体种子层并通过在低于600℃的温度的无定形工艺条件下将硅直接沉积在多晶硅籽晶层上形成硅层。

公开(公告)号：US11127733B2

公开(公告)日：2021-09-21

申请号：US16783188

申请日：2020-02-06

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.