公开(公告)号：US09992860B2

公开(公告)日：2018-06-05

申请号：US15138870

申请日：2016-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Benjamin Toby ,  Karl J. Bois

IPC: H02M3/06 ,  H05K1/02 ,  H05K1/18 ,  H05K1/11 ,  G06F17/50 ,  H05K3/00 ,  H03H7/00 ,  H01P3/08 ,  H02M3/22

CPC classification number: H05K1/025 ,  G06F17/5063 ,  G06F17/5068 ,  H01P3/081 ,  H03H7/004 ,  H05K1/0245 ,  H05K1/111 ,  H05K1/181 ,  H05K3/0005 ,  H05K2201/10015

Abstract: One example includes a printed circuit board (PCB) structure. The PCB structure includes a first dereferenced microstrip and a first capacitor pad contacting the first dereferenced microstrip. The PCB structure includes a second dereferenced microstrip and a second capacitor pad contacting the second dereferenced microstrip. The PCB structure also includes a capacitor including a first terminal contacting the first capacitor pad and a second terminal contacting the second capacitor pad.

公开(公告)号：US20190021164A1

公开(公告)日：2019-01-17

申请号：US15650223

申请日：2017-07-14

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Karl J. Bois ,  Elene Chobanyan ,  Benjamin Toby

IPC: H04B3/28 ,  H05K1/02 ,  H05K9/00

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer. A void of a defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines. A resistive material of the defected ground structure along a perimeter of the void improves suppression of the EMI propagated by the strip lines, via the resistive material absorbing the EMI.

公开(公告)号：US10178761B2

公开(公告)日：2019-01-08

申请号：US15141131

申请日：2016-04-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Karl J. Bois ,  Benjamin Toby

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.

公开(公告)号：US20170318665A1

公开(公告)日：2017-11-02

申请号：US15141131

申请日：2016-04-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Karl J. Bois ,  Benjamin Toby

IPC: H05K1/02 ,  H05K3/10 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/0245 ,  H05K1/0225 ,  H05K1/0298 ,  H05K1/115

Abstract: A multiple-layer circuit board has a signaling layer, an exterior layer, and a ground layer. A pair of differential signal lines implemented as strip lines are within the signaling layer, and propagate electromagnetic interference (EMI) along the signaling layer. An element conductively extends inwards from the exterior layer, and as an antenna radiates the EMI propagated by the strip lines along the signaling layer outwards from the circuit board. A defected ground structure within the ground layer has a size, shape, and a location in relation to the element to suppress the EMI propagated by the strip lines to minimize the EMI that the element radiates outwards as the antenna.

公开(公告)号：US10372857B2

公开(公告)日：2019-08-06

申请号：US15138858

申请日：2016-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Benjamin Toby ,  Karl J. Bois

IPC: G06F17/50

Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.

公开(公告)号：US20170311434A1

公开(公告)日：2017-10-26

申请号：US15138870

申请日：2016-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Benjamin Toby ,  Karl J. Bois

IPC: H05K1/02 ,  H05K3/00 ,  H01P3/08 ,  G06F17/50 ,  H03H7/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/025 ,  G06F17/5063 ,  G06F17/5068 ,  H01P3/081 ,  H03H7/004 ,  H05K1/0245 ,  H05K1/111 ,  H05K1/181 ,  H05K3/0005 ,  H05K2201/10015

Abstract: One example includes a printed circuit board (PCB) structure. The PCB structure includes a first dereferenced microstrip and a first capacitor pad contacting the first dereferenced microstrip. The PCB structure includes a second dereferenced microstrip and a second capacitor pad contacting the second dereferenced microstrip. The PCB structure also includes a capacitor including a first terminal contacting the first capacitor pad and a second terminal contacting the second capacitor pad.

公开(公告)号：US20170308627A1

公开(公告)日：2017-10-26

申请号：US15138858

申请日：2016-04-26

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Benjamin Toby ,  Karl J. Bois

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5063 ,  G06F17/5081

Abstract: One example includes a machine-readable storage medium encoded with instructions. The instructions are executable by a processor of a system to cause the system to receive at least one target electrical characteristic indicating a target impedance of a passive printed circuit board (PCB) structure. The passive PCB structure is a component of a serial communication channel. The instructions are executable by the processor to cause the system to divide the passive PCB structure into a plurality of elements. Each element has an input and an output. The instructions are executable by the processor to cause the system to determine at least one parameter of each element such that an image impedance of the input and the output of each element equals the target impedance.

公开(公告)号：US09712263B1

公开(公告)日：2017-07-18

申请号：US15254098

申请日：2016-09-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Karl J. Bois ,  Benjamin Toby ,  David P. Kopp

IPC: H04L1/20 ,  H04B17/336 ,  H04L12/26

CPC classification number: H04B17/336 ,  H04B17/318 ,  H04L1/203 ,  H04L1/242

Abstract: An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slices by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a bit error ratio based on the digital output signal and determining a confidence level for the measured bit error ratio, and in response to the determined confidence level equaling or exceeding a specified value, designating a current value of the measured bit-error ratio as the expected bit error ratio for the corresponding time-voltage slice and ending the test operation.