公开(公告)号：US09373614B2

公开(公告)日：2016-06-21

申请号：US13575579

申请日：2011-01-10

Applicant: Frederic Roger ,  Wolfgang Reinprecht

Inventor： Frederic Roger ,  Wolfgang Reinprecht

IPC: H01L27/02 ,  H01L27/07 ,  H01L27/06

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L27/067 ,  H01L27/0727

Abstract: A diode (23) is arranged near a transistor (25) to protect from ESD. The diode comprises a well (5) of a first conductivity type and a doped region (4) of a second conductivity type in opposition to the first conductivity type. The transistor comprises a doped well (2) and a doped region (1) of the first conductivity type. The well (2) of the transistor is doped lower than the well (5) of the diode.

Abstract translation: 二极管（23）布置在晶体管（25）附近以防止ESD。 二极管包括第一导电类型的阱（5）和与第一导电类型相反的第二导电类型的掺杂区域（4）。 晶体管包括掺杂阱（2）和第一导电类型的掺杂区域（1）。 晶体管的阱（2）的掺杂比二极管的阱（5）低。

公开(公告)号：US08525266B2

公开(公告)日：2013-09-03

申请号：US13407575

申请日：2012-02-28

Applicant: Wolfgang Reinprecht ,  Frederic Roger

Inventor： Wolfgang Reinprecht ,  Frederic Roger

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L27/0207

Abstract: A semiconductor body comprising a first connection for feeding an upper supply potential and a first and a second terminal cell, which are situated at a distance from each other. The semiconductor body further comprises an arrester structure, which is arranged between the first and second terminal cells in a p-doped substrate. The arrester structure comprises a first and a second p-channel field-effect transistor structure, each of which is set in a respective n-doped well substantially parallel to the first and second terminal cells, and a diode structure with a p-doped region set in a further n-doped well between the n-doped wells of the first and second p-channel field-effect transistor structures. The diode structure is designed to activate the first and second p-channel field-effect transistor structure as arrester elements during an electrostatic discharge in the semiconductor body.

Abstract translation: 一种半导体本体，包括用于馈送上电源的第一连接和位于彼此间隔一定距离的第一和第二端子单元。 半导体本体还包括一个放电器结构，它被布置在p掺杂衬底中的第一和第二端子单元之间。 避雷器结构包括第一和第二p沟道场效应晶体管结构，其每一个被设置在基本上平行于第一和第二端子单元的相应的n掺杂阱中，以及具有p掺杂区的二极管结构 设置在第一和第二p沟道场效应晶体管结构的n个掺杂阱之间的另一n掺杂阱中。 二极管结构被设计成在半导体主体中的静电放电期间激活第一和第二p沟道场效应晶体管结构作为避雷器元件。

公开(公告)号：US08373487B1

公开(公告)日：2013-02-12

申请号：US13220480

申请日：2011-08-29

Applicant: Frederic Roger

Inventor： Frederic Roger

IPC: G06F7/64

CPC classification number: G01R19/02 ,  G01R21/01

Abstract: Systems and methods are provided for power measurement of signals such that the power measurement is insensitive to PVT variations of the measurement systems. A power measurement system includes an analog squarer circuitry, an integrating ADC, and a controller. The squarer circuitry calculates the power of a signal whose power is to be measured while the integrating ADC integrates the calculated power over a runup interval to generate an integrated power. The squarer circuitry also calculates the power of a reference for the integrating ADC to de-integrate the integrated power over a rundown interval. The power measurements are independent of PVT variations of the analog squarer circuitry and integrating ADC. The controller digitally controls the runup interval and measures the rundown interval to provide digitized power measurements. The analog squarer circuitry have replica squarer circuits. Process dependent mismatches between the replica analog circuitry may be removed through a calibration process.

Abstract translation: 提供系统和方法用于信号的功率测量，使得功率测量对测量系统的PVT变化不敏感。 功率测量系统包括模拟平方电路，积分ADC和控制器。 平方电路计算其功率要被测量的信号的功率，而积分ADC通过运行间隔积分计算出的功率以产生积分功率。 平方电路还计算积分ADC的参考功率，以在整个时间间隔内对积分功率进行去积分。 功率测量与模拟平方电路和积分ADC的PVT变化无关。 控制器以数字方式控制延时间隔，并测量故障间隔以提供数字化功率测量。 模拟平方电路具有复制平方电路。 可以通过校准过程去除复制模拟电路之间的过程相关的不匹配。

公开(公告)号：US08295394B1

公开(公告)日：2012-10-23

申请号：US12257292

申请日：2008-10-23

Applicant: Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

Inventor： Adric Q. Broadwell ,  Armando C. Cova ,  Frederic Roger ,  Qian Yu

IPC: H04K1/02

CPC classification number: H03F1/3247 ,  H03F2201/3224

Abstract: A performance monitor for generating a digital error signal based upon an RF input signal and an amplified RF output signal is provided. The monitor includes: a first analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase (Q) version of the RF input signal responsive to a first clock signal to provide a first digital I signal and a first digital Q signal; a second analog-to-digital converter operable to digitize an in-phase (I) and a quadrature-phase version of the amplified RF output signal responsive to a second clock signal to provide a second digital I signal and a second digital Q signal; a first adaptive delay filter to delay the first digital I signal and the first digital Q signal to provide a first delayed complex signal according to a first delay; a second adaptive filter to delay the second digital I signal and the second digital Q signals to provide a second delayed complex signal according to a second delay; a complex gain matching adder operable to add a complex gain matching factor to a selected one of the delayed complex signals to provide a gain matched complex signal; and an adder to add the gain matched complex signal to a remaining one of the first and second delayed complex signals to provide the digital error signal.

Abstract translation: 提供了一种用于基于RF输入信号和放大的RF输出信号产生数字误差信号的性能监视器。 监视器包括：第一模数转换器，用于响应于第一时钟信号数字化RF输入信号的同相（I）和正交相位（Q）版本，以提供第一数字I信号和 第一数字Q信号; 第二模数转换器，用于响应于第二时钟信号数字化放大的RF输出信号的同相（I）和正交相位版本，以提供第二数字I信号和第二数字Q信号; 第一自适应延迟滤波器，用于延迟第一数字I信号和第一数字Q信号，以根据第一延迟提供第一延迟复信号; 第二自适应滤波器，用于延迟所述第二数字I信号和所述第二数字Q信号，以根据第二延迟提供第二延迟复信号; 复增益匹配加法器，用于将复增益匹配因子添加到所选延迟复信号中的一个以提供增益匹配复信号; 以及加法器，用于将增益匹配复信号与第一和第二延迟复数信号中的剩余的一个相加，以提供数字误差信号。

公开(公告)号：US20120211842A1

公开(公告)日：2012-08-23

申请号：US13407575

申请日：2012-02-28

Applicant: Wolfgang REINPRECHT ,  Frederic Roger

Inventor： Wolfgang REINPRECHT ,  Frederic Roger

IPC: H01L27/092

CPC classification number: H01L27/0266 ,  H01L27/0207

Abstract: A semiconductor body comprising a first connection for feeding an upper supply potential and a first and a second terminal cell, which are situated at a distance from each other. The semiconductor body further comprises an arrester structure, which is arranged between the first and second terminal cells in a p-doped substrate. The arrester structure comprises a first and a second p-channel field-effect transistor structure, each of which is set in a respective n-doped well substantially parallel to the first and second terminal cells, and a diode structure with a p-doped region set in a further n-doped well between the n-doped wells of the first and second p-channel field-effect transistor structures. The diode structure is designed to activate the first and second p-channel field-effect transistor structure as arrester elements during an electrostatic discharge in the semiconductor body.

Abstract translation: 一种半导体本体，包括用于馈送上电源的第一连接和位于彼此间隔一定距离的第一和第二端子单元。 半导体本体还包括一个放电器结构，它被布置在p掺杂衬底中的第一和第二端子单元之间。 避雷器结构包括第一和第二p沟道场效应晶体管结构，其每一个被设置在基本上平行于第一和第二端子单元的相应的n掺杂阱中，以及具有p掺杂区的二极管结构 设置在第一和第二p沟道场效应晶体管结构的n个掺杂阱之间的另一n掺杂阱中。 二极管结构被设计成在半导体主体中的静电放电期间激活第一和第二p沟道场效应晶体管结构作为避雷器元件。

公开(公告)号：US20100156471A1

公开(公告)日：2010-06-24

申请号：US12340307

申请日：2008-12-19

Applicant: Frederic Roger

Inventor： Frederic Roger

IPC: H02M11/00

CPC classification number: H03F3/45183 ,  H03F1/3211 ,  H03F1/3241 ,  H03F2200/336 ,  H03F2201/3209

Abstract: A cost function generator circuit includes memory terms each receiving one or more input signals, and each providing inphase and quadrature output current signals. The inphase and quadrature output currents of the memory terms are summed to provide combined inphase and quadrature output currents, respectively. Transimpedance amplifiers are provided to transform the combined inphase and quadrature output currents into an inphase output voltage and a quadrature output voltage.

Abstract translation: 成本函数发生器电路包括各自接收一个或多个输入信号的存储器项，并且每个都提供同相和正交输出电流信号。 存储器项的同相和正交输出电流被相加以分别提供组合的同相和正交输出电流。 提供互阻抗放大器以将组合的同相和正交输出电流转换为同相输出电压和正交输出电压。

公开(公告)号：US20050062629A1

公开(公告)日：2005-03-24

申请号：US10493298

申请日：2002-07-18

Applicant: Frederic Roger ,  Ralf-Rainer Schledz

Inventor： Frederic Roger ,  Ralf-Rainer Schledz

IPC: H03M1/68 ,  H03M1/66

CPC classification number: H03M1/68

Abstract: A digital/analog converter apparatus (DAC) comprises, for the purpose of converting a digital input signal (D) into an analog output signal (A), a first unit (F1, F2), two digital/analog converters (DAC1, DAC2) and a second unit (K1, K2), which are connected successively in the stated order. From the digital input signal (D), digital intermediate signals (D1, D2) which are within the analog output signal (A) is obtained through linear combination.

Abstract translation: 为了将数字输入信号（D）转换为模拟输出信号（A），数字/模拟转换器装置（DAC）包括第一单元（F1，F2），两个数模转换器（DAC1，DAC2 ）和第二单元（K1，K2），其以所述顺序连续连接。 通过数字输入信号（D），通过线性组合获得模拟输出信号（A）内的数字中间信号（D1，D2）。

公开(公告)号：US20130113036A1

公开(公告)日：2013-05-09

申请号：US13575579

申请日：2011-01-10

Applicant: Frederic Roger ,  Wolfgang Reinprecht

Inventor： Frederic Roger ,  Wolfgang Reinprecht

IPC: H01L27/02

CPC classification number: H01L27/0255 ,  H01L27/0629 ,  H01L27/067 ,  H01L27/0727

Abstract: A diode (23) is arranged near a transistor (25) to protect from ESD. The diode comprises a well (5) of a first conductivity type and a doped region (4) of a second conductivity type in opposition to the first conductivity type. The transistor comprises a doped well (2) and a doped region (1) of the first conductivity type. The well (2) of the transistor is doped lower than the well (5) of the diode.

Abstract translation: 二极管（23）布置在晶体管（25）附近以防止ESD。 二极管包括第一导电类型的阱（5）和与第一导电类型相反的第二导电类型的掺杂区域（4）。 晶体管包括掺杂阱（2）和第一导电类型的掺杂区域（1）。 晶体管的阱（2）的掺杂比二极管的阱（5）低。

公开(公告)号：US08433745B2

公开(公告)日：2013-04-30

申请号：US12340307

申请日：2008-12-19

Applicant: Frederic Roger

Inventor： Frederic Roger

IPC: G06G7/02

CPC classification number: H03F3/45183 ,  H03F1/3211 ,  H03F1/3241 ,  H03F2200/336 ,  H03F2201/3209

Abstract: A cost function generator circuit includes memory terms each receiving one or more input signals, and each providing inphase and quadrature output current signals. The inphase and quadrature output currents of the memory terms are summed to provide combined inphase and quadrature output currents, respectively. Transimpedance amplifiers are provided to transform the combined inphase and quadrature output currents into an inphase output voltage and a quadrature output voltage.

Abstract translation: 成本函数发生器电路包括各自接收一个或多个输入信号的存储器项，并且每个都提供同相和正交输出电流信号。 存储器项的同相和正交输出电流被相加以分别提供组合的同相和正交输出电流。 提供互阻抗放大器以将组合的同相和正交输出电流转换为同相输出电压和正交输出电压。

公开(公告)号：US08010075B1

公开(公告)日：2011-08-30

申请号：US12037455

申请日：2008-02-26

Applicant: Frederic Roger

Inventor： Frederic Roger

IPC: H04B1/26

CPC classification number: H03F1/3247 ,  H03F1/3241 ,  H03F2200/102 ,  H03F2200/105 ,  H04B2001/0425

Abstract: A high-order harmonics generator includes a plurality of high-pass filters to block out DC signals. In one embodiment, high-pass filters are coupled to the output signals from an envelope detector and a power detector. A high-pass filter can also be coupled to the output of a multiplier that multiplies the filtered envelope signal and the filtered power signal. Additional multipliers may also be used at outputs of multipliers in a cascaded chain of multipliers for higher harmonics generation.

Abstract translation: 高次谐波发生器包括多个高通滤波器以阻断DC信号。 在一个实施例中，高通滤波器耦合到来自包络检测器和功率检测器的输出信号。 高通滤波器也可以耦合到乘法器的输出，乘法器将滤波的包络信号和滤波的功率信号相乘。 另外的乘法器也可以用于级联的乘法器链中用于较高次谐波产生的乘法器的输出。