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公开(公告)号:US11323729B2
公开(公告)日:2022-05-03
申请号:US17129424
申请日:2020-12-21
Applicant: Coherent Logix, Incorporated
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah , John C. Sievers
IPC: H04N19/436 , G06F9/38 , H04N19/176 , H04N19/146 , H04N19/107 , H04N19/147
Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
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公开(公告)号:US11544895B2
公开(公告)日:2023-01-03
申请号:US16582325
申请日:2019-09-25
Applicant: COHERENT LOGIX, INCORPORATED
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah
Abstract: Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.
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公开(公告)号:US20210152839A1
公开(公告)日:2021-05-20
申请号:US17129424
申请日:2020-12-21
Applicant: Coherent Logix, Incorporated
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah , John C. Sievers
IPC: H04N19/436 , G06F9/38 , H04N19/176 , H04N19/146 , H04N19/107 , H04N19/147
Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
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公开(公告)号:US11849130B2
公开(公告)日:2023-12-19
申请号:US17733678
申请日:2022-04-29
Applicant: Coherent Logix, Incorporated
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah , John C. Sievers
IPC: H04N19/43 , H04N19/436 , G06F9/38 , H04N19/176 , H04N19/146 , H04N19/107 , H04N19/147
CPC classification number: H04N19/436 , G06F9/3877 , H04N19/107 , H04N19/146 , H04N19/147 , H04N19/176
Abstract: Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
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公开(公告)号:US20190182495A1
公开(公告)日:2019-06-13
申请号:US16216967
申请日:2018-12-11
Applicant: Coherent Logix, Incorporated
Inventor: Michael W. Bruns , Michael A. Hunt , Manjunath H. Siddaiah , John C. Sievers
IPC: H04N19/436 , G06F9/38 , H04N19/107 , H04N19/146 , H04N19/176
Abstract: Methods and devices are described for a parallel multi-processor encoder system for encoding video data, wherein the video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system may divide the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks may be transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
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公开(公告)号:US20220264130A1
公开(公告)日:2022-08-18
申请号:US17733678
申请日:2022-04-29
Applicant: Coherent Logix, Incorporated
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah , John C. Sievers
IPC: H04N19/436 , G06F9/38 , H04N19/176 , H04N19/146 , H04N19/107 , H04N19/147
Abstract: Methods and devices for a parallel multi-processor encoder system for encoding video data. The video data comprises a sequence of frames, wherein each frame comprises a plurality of blocks of pixels in sequential rows. For each frame, the system divides the plurality of blocks into a plurality of subsets of blocks, wherein each subset of blocks is allocated to a respective processor of the parallel multi-processor system. Each respective processor of the parallel multi-processor system may sequentially encode rows of the subset of blocks allocated to the respective processor and sequentially transmit each encoded row of blocks as a bit stream to a decoder on a channel. For each row, the respective encoded row of blocks is transmitted to the decoder for each processor prior to transmission of the next sequential respective encoded row of blocks for any processor. Additionally, a similar parallel multi-processor decoder system is described.
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公开(公告)号:US20200098164A1
公开(公告)日:2020-03-26
申请号:US16582325
申请日:2019-09-25
Applicant: COHERENT LOGIX, INCORPORATED
Inventor: Michael W. Bruns , Martin A. Hunt , Manjunath H. Siddaiah
Abstract: Methods and systems for rendering an output image from a plurality of input images. The plurality of input images is received, and each input image is taken from a different first location. A view specification for rendering the output image is received, and the view specification includes at least a second location. The second location is different from each of the first locations. An output image is rendered based at least in part on the plurality of input images and the view specification, and the output image includes an image of a region as seen from the second location. The output image is displayed on a display.