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公开(公告)号：US08374038B2
公开(公告)日：2013-02-12
申请号：US12773503
申请日：2010-05-04
Applicant: Chuan-Ying Yu , Chun-Hsiung Hung , Ken-Hui Chen
Inventor： Chuan-Ying Yu , Chun-Hsiung Hung , Ken-Hui Chen
IPC: G11C11/34
CPC classification number: G11C16/16 , G11C16/0483
Abstract: A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.
Abstract translation: 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。
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2.发明授权Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control 有权使用改进的参考细胞修剪算法的存储器件和方法用于精确的读操作窗口控制
公开(公告)号：US08094493B2
公开(公告)日：2012-01-10
申请号：US11271300
申请日：2005-11-10
Applicant: Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
Inventor： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
CPC classification number: G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/028 , G11C29/24 , G11C29/50004 , G11C2211/5634
Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).
Abstract translation: 公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。 存储装置还包括多个参考线和参考单元。 每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。 来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考 当前修剪）。
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公开(公告)号：US20110273936A1
公开(公告)日：2011-11-10
申请号：US12773503
申请日：2010-05-04
Applicant: Chuan-Ying Yu , Chun-Hsiung Hung , Ken-Hui Chen
Inventor： Chuan-Ying Yu , Chun-Hsiung Hung , Ken-Hui Chen
CPC classification number: G11C16/16 , G11C16/0483
Abstract: A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased.
Abstract translation: 擦除存储器件的存储器单元的方法包括如果擦除过程被暂停，则对存储器单元进行编程。 擦除过程可以包括对所选存储器单元中的存储器单元的预编程，擦除和软编程。 如果接收到暂停命令，例如允许对另一个存储单元的存储单元进行读操作，则擦除过程停止预编程，擦除或软编程，并且继续编程一个或多个存储器单元 被擦除的内存单元。
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公开(公告)号：US09225240B2
公开(公告)日：2015-12-29
申请号：US12786122
申请日：2010-05-24
Applicant: Chun-Hsiung Hung , Chuan-Ying Yu
Inventor： Chun-Hsiung Hung , Chuan-Ying Yu
CPC classification number: H02M3/073
Abstract: A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.
Abstract translation: 在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。 接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。 然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。 泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。
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公开(公告)号：US08482987B2
公开(公告)日：2013-07-09
申请号：US12875003
申请日：2010-09-02
Applicant: Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
Inventor： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
IPC: G11C16/04
CPC classification number: G11C16/16 , G11C16/345 , G11C16/3454
Abstract: Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
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公开(公告)号：US08203896B2
公开(公告)日：2012-06-19
申请号：US12911173
申请日：2010-10-25
Applicant: Kuen-Long Chang , Chun-Hsiung Hung , Chuan-Ying Yu , Chun-Yi Lee
Inventor： Kuen-Long Chang , Chun-Hsiung Hung , Chuan-Ying Yu , Chun-Yi Lee
CPC classification number: G11C29/022 , G11C29/02
Abstract: A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip.
Abstract translation: 提供了一种存储芯片及其操作方法。 存储器芯片包括多个焊盘。 该方法包括分别将多个第一测试信号输入到焊盘，其中对应于两个物理相邻的焊盘的第一测试信号是互补的; 将多个分别连续到第一测试信号的第二测试信号输入到焊盘，其中对应于每个焊盘的第一测试信号和第二测试信号是互补的; 以及如果所述第一测试信号和所述第二测试信号被所述存储芯片成功接收，则从所述存储器芯片输出预期数据。
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公开(公告)号：US20110115551A1
公开(公告)日：2011-05-19
申请号：US12786122
申请日：2010-05-24
Applicant: Chun-Hsiung Hung , Chuan-Ying Yu
Inventor： Chun-Hsiung Hung , Chuan-Ying Yu
IPC: G05F3/02
CPC classification number: H02M3/073
Abstract: A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage.
Abstract translation: 在集成电路中产生泵浦电压的方法包括从集成电路的外部接收外部时钟信号。 接收到的外部时钟信号的频率根据一个或多个调制比而改变，导致一个或多个相应调制的外部时钟信号。 然后选择外部时钟信号或调制的外部时钟信号之一用作泵浦时钟信号。 泵时钟信号用于驱动泵电路的泵电容以产生泵浦电压。
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公开(公告)号：US20110069571A1
公开(公告)日：2011-03-24
申请号：US12816960
申请日：2010-06-16
Applicant: Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
Inventor： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
CPC classification number: G11C16/16
Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
Abstract translation: 该技术的一个实施例是一种装置，存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。
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公开(公告)号：US20070019470A1
公开(公告)日：2007-01-25
申请号：US11188505
申请日：2005-07-25
Applicant: Chun-Hsiung Hung , Chuan-Ying Yu
Inventor： Chun-Hsiung Hung , Chuan-Ying Yu
IPC: G11C16/04
CPC classification number: G11C16/3468 , G11C16/12 , G11C16/3404
Abstract: A flash based device in configured for soft programming to correct for over-erase effect; however, the soft programming current is limited so as not to exceed the current that can be supplied during soft programming. Additionally, the voltage on the source node of each cell on the flash based device is maintained at a non-zero level, in order to allow for the use fo a higher word line voltage, but help prevent an over soft programming effect.
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公开(公告)号：US07355903B2
公开(公告)日：2008-04-08
申请号：US11181983
申请日：2005-07-15
Applicant: Chun-Hsiung Hung , Chuan-Ying Yu , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Kuen-Long Chang
Inventor： Chun-Hsiung Hung , Chuan-Ying Yu , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Kuen-Long Chang
IPC: G11C7/10
CPC classification number: G11C16/24
Abstract: A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.
Abstract translation: 一种半导体器件，包括具有控制栅极，源极和漏极的存储单元; 以及耦合到源极的限流电路。 电流限制电路可以被配置为将漏极和源极之间的电流限制为不超过预定值; 响应于分别向控制栅极和漏极施加第一和第二电压而产生电流。 电流限制电路可以包括包括第一端子，第二端子和第三端子的晶体管，其中第一端子可以包括晶体管的源极，第三端子可以包括晶体管的漏极，并且第二端子可以 包括晶体管的栅极，并且其中可以将稳定的偏压施加到晶体管的第二端子。
