公开(公告)号：US11212803B2

公开(公告)日：2021-12-28

申请号：US16814512

申请日：2020-03-10

Applicant: Apple Inc.

Inventor： Adam B. Lapede ,  Daniel R. Borges ,  Mohammed W. Mokhtar ,  Helena D. O'Shea ,  Alon Paycher ,  Oren Shani ,  Matthew L. Semersky ,  Sriram Hariharan ,  Sreeraman Anantharaman ,  Khaye Loon Wei ,  Andrew D. Smart

IPC: H04W72/04 ,  H04W36/06 ,  H04B10/516 ,  H04L1/00 ,  H03H21/00

Abstract: Disclosed herein are system, method, and computer program product embodiments for synchronizing the switching of different wireless platforms to different portions of a frequency band. An embodiment, at a first wireless platform, operates by receiving a band switch request message from a second wireless platform, wherein the band switch request message comprises a band switch delay period for the second wireless platform. The embodiment calculates a band switch time based on a band switch delay period for the first wireless platform and the band switch delay period for the second wireless platform. The embodiment transmits a band switch accept message comprising the band switch time to the second wireless platform. The embodiment sets a first filter to operate on a second portion of the frequency band based on the band switch time. The embodiment then operates on the second portion of the frequency band.

公开(公告)号：US20200213516A1

公开(公告)日：2020-07-02

申请号：US16730859

申请日：2019-12-30

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  H04N7/10 ,  H04N5/225 ,  H04N7/01 ,  H04L29/08 ,  G06F3/14

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US11064387B1

公开(公告)日：2021-07-13

申请号：US16411302

申请日：2019-05-14

Applicant: Apple Inc.

Inventor： Aleksandr M. Movshovich ,  Arthur Y. Zhang ,  Hao Pan ,  Holly E. Gerhard ,  Jim C. Chou ,  Moinul H. Khan ,  Paul V. Johnson ,  Sorin C. Cismas ,  Sreeraman Anantharaman ,  William W. Sprague

IPC: H04W28/06 ,  H04W24/08 ,  H04N13/398 ,  H04N13/344 ,  H04N13/194

Abstract: One exemplary implementation involves performing operations at an electronic device with one or more processors and a computer-readable storage medium. The device establishes a wireless communication link with a host device. The device receives, from the host device, a left eye frame and a right eye frame via a sequence of left eye frame transmissions and right eye frame transmissions. The device switches data transmissions schemes according to wireless commination link quality or eye gaze tracking. Adjusting transmission format based on transmission quality of the wireless communication link allows the devices to take advantage of greater bandwidth when available to save power. An additional transmission format is based on alternately transmitting left eye and right eye frames for very low bandwidth.

公开(公告)号：US10592460B2

公开(公告)日：2020-03-17

申请号：US16241781

申请日：2019-01-07

Applicant: Apple Inc.

Inventor： Colin Whitby-Strevens ,  Sreeraman Anantharaman

IPC: G06F13/42 ,  G09G5/00 ,  H04N21/4223 ,  H04N21/426 ,  H04N5/232

Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

公开(公告)号：US20170359513A1

公开(公告)日：2017-12-14

申请号：US15620595

申请日：2017-06-12

Applicant: APPLE INC.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  H04N5/225 ,  H04N7/10 ,  H04N7/01 ,  H04L29/08

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US11258947B2

公开(公告)日：2022-02-22

申请号：US16730859

申请日：2019-12-30

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Hyuck-Jae Lee ,  Vincent Wang

IPC: H04N5/232 ,  G06F3/14 ,  H04L29/08 ,  H04N7/01 ,  H04N5/225 ,  H04N7/10 ,  H04L69/324

Abstract: Methods and apparatus for link training and low power operation. A multi-lane high speed bus is optimized for transferring audio/visual (A/V) data at slower rates. In one embodiment, the high speed bus is configured to use a packet format structure that allows for more fluid data delivery times, thereby allowing the high speed bus to deliver A/V data at times selected to reduce power consumption. In another embodiment, the high speed bus is configured to cache link initialization data for subsequent link re-initialization before entering a low power state. Thereafter, when the link exits the low power state, the high speed bus can skip certain portions of link initialization. Still a third embodiment of the present disclosure is directed to exemplary modifications to existing high speed bus link training and low power operation, consistent with the aforementioned principles. Variants of a Universal Serial Bus implementation are provided for illustration.

公开(公告)号：US10459674B2

公开(公告)日：2019-10-29

申请号：US14566554

申请日：2014-12-10

Applicant: APPLE INC.

Inventor： Colin Whitby-Strevens ,  Sreeraman Anantharaman

IPC: G06F3/14

Abstract: Methods and apparatus for packing and transporting data within an electronic device. In one embodiment, a consumer electronics device having one or more sensors (e.g., camera sensors) uses modified DisplayPort micro-packets for transmission of RAW format data over one or more lanes of a DisplayPort Main Steam. The RAW data is transported over the one or more lanes by mapping symbol sequences generated from the RAW data based on Y-only data mappings schemes of DisplayPort. A mapping scheme is in one variant selected based on the bits length (e.g., bits per pixel) of the RAW data, in addition to the number of lanes used to transport over the Main Stream. In order for the sink correctly unpack received the micro-packets, the transmitting source transmits Main Stream Attribute (MSA) data packets configured to indicate at least the mapping scheme used.

公开(公告)号：US10176141B2

公开(公告)日：2019-01-08

申请号：US15894719

申请日：2018-02-12

Applicant: APPLE INC.

Inventor： Colin Whitby-Strevens ,  Sreeraman Anantharaman

IPC: G06F13/42 ,  G09G5/00 ,  H04N21/4223 ,  H04N21/426 ,  H04N5/232

Abstract: Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.

公开(公告)号：US20170287102A1

公开(公告)日：2017-10-05

申请号：US15627192

申请日：2017-06-19

Applicant: Apple Inc.

Inventor： Sreeraman Anantharaman ,  Colin Whitby-Strevens

IPC: G06T1/20 ,  G09G5/00

Abstract: Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.

公开(公告)号：US09070199B2

公开(公告)日：2015-06-30

申请号：US13658686

申请日：2012-10-23

Applicant: Apple Inc.

Inventor： William O. Ferry ,  David J. Redman ,  Adrian T. Sheppard ,  Sreeraman Anantharaman

IPC: G06F3/14 ,  G06T1/20 ,  G09G5/00

CPC classification number: G06F3/1431 ,  G06F13/385 ,  G06T1/20 ,  G09G5/006 ,  G09G2360/02 ,  G09G2360/04 ,  G09G2370/042 ,  G09G2370/045 ,  G09G2370/12

Abstract: An electronic device selectively couples a head with links in a graphics processing unit to a currently selected display port in a pair of display ports. During operation, control logic in the electronic device monitors a pair of configuration signals from the pair of display ports, where the pair of configuration signals correspond to physical connections to the pair of display ports. Then, the control logic determines a selection control signal based on the monitored pair of configuration signals, a policy setting and a default display port, where the selection control signal specifies the currently selected display port. Moreover, the control logic provides the selection control signal to a multiplexer in the electronic device. Next, the multiplexer selectively couples the head with the links in the graphics processing unit to the currently selected display port based on the selection control signal.

Abstract translation: 电子设备将头部与图形处理单元中的链路选择性地耦合到一对显示端口中的当前选择的显示端口。 在操作期间，电子设备中的控制逻辑监视来自该对显示端口的一对配置信号，其中该对配置信号对应于到该对显示端口的物理连接。 然后，控制逻辑基于所监视的一对配置信号，策略设置和默认显示端口来确定选择控制信号，其中选择控制信号指定当前选择的显示端口。 此外，控制逻辑将选择控制信号提供给电子设备中的多路复用器。 接下来，多路复用器基于选择控制信号将头部与图形处理单元中的链路选择性地耦合到当前选择的显示端口。