公开(公告)号：US20160267867A1

公开(公告)日：2016-09-15

申请号：US14832600

申请日：2015-08-21

Applicant: Apple Inc.

Inventor： James E. C. Brown

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0291

Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.

Abstract translation: 用于显示面板的栅极线驱动电路包括一个上拉电路，用于将显示面板的栅极线驱动到正电压，该正电压使得耦合到栅极线的显示面板开关元件转变成导通状态;第一拉 以将栅极线驱动到导致耦合的显示面板开关元件转变到截止状态的第一负电压，以及第二下拉晶体管，以将栅极线保持在比第一负电压小的第二负电压 负电压，以使耦合的显示面板开关元件保持在关闭状态。 还描述和要求保护其他实施例。

公开(公告)号：US09805681B2

公开(公告)日：2017-10-31

申请号：US14832600

申请日：2015-08-21

Applicant: Apple Inc.

Inventor： James E. C. Brown

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2310/0291

Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.

公开(公告)号：US09946101B2

公开(公告)日：2018-04-17

申请号：US14835366

申请日：2015-08-25

Applicant: Apple Inc.

Inventor： James E. C. Brown ,  Fenghua Zheng ,  Sandro H. Pintz

IPC: G09G3/36 ,  G02F1/133

CPC classification number: G02F1/13306 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0289

Abstract: A method for operating a gate driver that is driving pixel transistors of a display panel, is described. An internal start pulse is produced in response to an external start pulse and in accordance with a system clock, wherein the internal start pulse is input to a first cell of a gate driver shift register whose outputs are coupled to level shifting output stages that are driving the rows of pixel transistors of the display panel. The produced internal start pulse was qualified by an output of a last cell of the gate driver shift register. Other embodiments are also described and claimed.

公开(公告)号：US20160300546A1

公开(公告)日：2016-10-13

申请号：US14855733

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Fenghua Zheng ,  Christopher P. Tann ,  David S. Zalatimo ,  James E. C. Brown ,  Sandro H. Pintz

IPC: G09G5/00

CPC classification number: G09G3/2096 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/06 ,  G09G2310/08 ,  G09G2330/021

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.

Abstract translation: 显示器可以具有由显示驱动器电路控制的像素阵列。 栅极驱动器电路将栅极线信号提供给像素的行。 栅极驱动器电路可以包括栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有将栅极线信号提供给像素行的移位寄存器。 显示驱动器电路将时钟信号提供给栅极驱动器集成电路。 每个栅极驱动器集成电路可以具有选择性地使能和禁止的一个或多个时钟树。 每个栅极驱动器集成电路可以具有由来自控制器的控制信号控制的控制器和缓冲器。 可以调整缓冲器以提供或不向该栅极驱动器集成电路中的相关联的时钟树提供时钟信号。

公开(公告)号：US10276085B2

公开(公告)日：2019-04-30

申请号：US14973517

申请日：2015-12-17

Applicant: Apple Inc.

Inventor： Chaohao Wang ,  Paolo Sacchetto ,  Marc Albrecht ,  Christopher P. Tann ,  Shih-Chyuan Fan Jiang ,  Howard H. Tang ,  James E. C. Brown ,  Zhibing Ge

IPC: G09G3/20

Abstract: This application relates to systems, methods, and apparatus for compensating voltage for pixels of a display panel based on the location of the pixels within the display panel. An amount of voltage compensation is assigned to each pixel or a group of pixels within the display panel in accordance with a calibration of the display panel. During operation of the display panel, pixel data is generated for a location of the display panel, and the pixel data is modified according to the amount of voltage compensation corresponding to the location. By modifying the pixel data in this way, spatial variations in voltage across the display panel can be mitigated in order to reduce the occurrence of certain display artifacts at the display panel.

公开(公告)号：US10163385B2

公开(公告)日：2018-12-25

申请号：US14855733

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Fenghua Zheng ,  Christopher P. Tann ,  David S. Zalatimo ,  James E. C. Brown ,  Sandro H. Pintz

IPC: G09G5/00 ,  G09G3/20

Abstract: A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.