公开(公告)号：US20190155516A1

公开(公告)日：2019-05-23

申请号：US15818212

申请日：2017-11-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US10275352B1

公开(公告)日：2019-04-30

申请号：US15856430

申请日：2017-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G11C7/00 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G11C16/34 ,  G06F15/78 ,  G11C16/04 ,  G11C16/10 ,  G06F12/0897

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

公开(公告)号：US12204754B2

公开(公告)日：2025-01-21

申请号：US16959503

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US11422707B2

公开(公告)日：2022-08-23

申请号：US15851479

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James Raymond Magro

IPC: G06F13/16 ,  G06F9/50 ,  G06F3/06 ,  G06F12/10

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

公开(公告)号：US20190196721A1

公开(公告)日：2019-06-27

申请号：US15851479

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James Raymond Magro

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/5011 ,  G06F12/10 ,  G06F13/1626 ,  G06F13/1631 ,  G06F13/1684 ,  G06F2212/1024

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. A computing system includes one or more clients for processing applications. A memory controller transfers traffic between the memory controller and two channels, each connected to a memory device. A client sends a 64-byte memory request with an indication specifying that there are two 32-byte requests targeting non-contiguous data within a same page. The memory controller generates two addresses, and sends a single command and the two addresses to two channels to simultaneously access non-contiguous data in a same page.

公开(公告)号：US11474942B2

公开(公告)日：2022-10-18

申请号：US16959496

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G11C7/00 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0875 ,  G11C16/34 ,  G06F15/78 ,  G11C16/04 ,  G11C16/10 ,  G06F12/0897 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for identifying response data arriving out-of-order from two different memory types are disclosed. A computing system includes one or more clients for processing applications. A memory channel transfers memory traffic between a memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a given point in time when read data is to be scheduled to arrive on the memory bus from memory. The memory controller associates a unique identifier with the given point in time. The memory controller identifies a given command associated with the arriving read data based on the given point in time.

公开(公告)号：US11429281B2

公开(公告)日：2022-08-30

申请号：US16841514

申请日：2020-04-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US10296230B1

公开(公告)日：2019-05-21

申请号：US15853090

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/22 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US20220404978A1

公开(公告)日：2022-12-22

申请号：US17895357

申请日：2022-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Ravindra N. Bhargava ,  Philip S. Park ,  Vydhyanathan Kalyanasundharam ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

公开(公告)号：US11526278B2

公开(公告)日：2022-12-13

申请号：US15851414

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  James Raymond Magro ,  Kedarnath Balakrishnan ,  Kevin M. Brandl

IPC: G06F3/06

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.