Abstract:
Aspects of the subject technology relate to electronic device display circuitry and methods of operating the display. The display circuitry a panel driver interface that decodes digital display data, for each display frame, received from host circuitry of the electronic device. The digital display data includes error correction and detection information for frame and line configuration information distributed in a frame packet and multiple line packets for each display frame. The frame and line configuration information facilitates, efficient, low-error, digital control of various display operational features.
Abstract:
Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.
Abstract:
A display may have an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The gate driver circuitry may include gate driver integrated circuits. Each gate driver integrated circuit may have a shift register that supplies the gate line signals to the rows of pixels. The display driver circuitry supplies a clock signal to the gate driver integrated circuits. Each gate driver integrated circuit may have one or more clock trees that are selectively enable and disabled. Each gate driver integrated circuit may have a controller and a buffer that is controlled by a control signal from the controller. The buffer may be adjusted to supply or to not supply the clock signal to an associated clock tree in that gate driver integrated circuit.
Abstract:
Devices and methods for reducing or eliminating spatiotemporal dithering image artifacts are provided. By way of example, a method includes providing positive polarity and negative polarity data signals to a plurality of pixels of a display during a first frame period, in which the first frame period corresponds a first spatiotemporal rotation phase. The method includes providing the positive polarity signals and the negative polarity signals to the plurality of pixels of the display during a second frame period, in which the second frame period corresponds a second spatiotemporal rotation phase. A spatiotemporal rotation phase sequence provided to the display comprises the first spatiotemporal rotation phase and the second spatiotemporal rotation phase. One of the first spatiotemporal rotation phase and the second spatiotemporal rotation phase of the spatiotemporal rotation phase sequence is altered during the first frame period or the second time period.
Abstract:
An electronic device may be provided with a display. The display may include a backlight having an array of locally dimmable light sources. Control circuitry may provide control signals to the backlight to produce light at different brightness levels. When the brightness level is below a threshold, the control circuitry may use pulse-width-modulation control signals to control the light sources in the backlight. When the brightness level is above the brightness threshold, the control circuitry may use analog control signals to control the light sources in the backlight. The control circuitry may adjust the threshold to achieve different dimming ranges for different brightness settings. A low brightness setting, for example, may have a lower threshold and lower dimming range than a high brightness setting, which may help produce darker darks when the display operates in a low brightness setting.
Abstract:
Methods and devices for reducing the power consumption of a frame buffer and timing controller of an electronic display are provided. By way of example, a method of operating an electronic display includes receiving image data from a processor of the electronic display, storing the image data to a buffer of the electronic display, reading the image data from the buffer to supply the image data to a column driver of the electronic display, determining whether an amount of image data stored in buffer is less than a threshold, and switching from reading the image data from the buffer to reading the image data directly from the processor when the amount of image data stored in buffer is less than the threshold.
Abstract:
An electronic device may generate content that is to be displayed on a display. The display may have an array of liquid crystal display pixels for displaying image frames of the content. The image frames may be displayed with positive and negative polarities to help reduce charge accumulation effects. A charge accumulation tracker may analyze the image frames to determine when there is a risk of excess charge accumulation. The charge accumulation tracker may analyze information on gray levels, frame duration, and frame polarity. The charge accumulation tracker may compute a charge accumulation metric for entire image frames or may process subregions of each frame separately. When subregions are processed separately, each subregion may be individually monitored for a risk of excess charge accumulation.
Abstract:
Devices and methods for reducing and/or substantially eliminating pixel charge imbalance due to variable refresh rates are provided. By way of example, a method includes providing a first frame of image data via a processor to a plurality of pixels of the display during a first frame period corresponding to a first refresh rate, and providing a second frame of image data to the plurality of pixels of the display during a second frame period corresponding to a second refresh rate. The method further includes dividing the first frame period into a first frame sub-period and a second frame sub-period, and driving the plurality of pixels of the display with the first frame of image data during the first frame sub-period and the second frame sub-period.
Abstract:
Methods and devices for reducing the power consumption of a frame buffer and timing controller of an electronic display are provided. By way of example, a method of operating an electronic display includes receiving image data from a processor of the electronic display, storing the image data to a buffer of the electronic display, reading the image data from the buffer to supply the image data to a column driver of the electronic display, determining whether an amount of image data stored in buffer is less than a threshold, and switching from reading the image data from the buffer to reading the image data directly from the processor when the amount of image data stored in buffer is less than the threshold.
Abstract:
An electronic device may include an electronic display having multiple display pixels to display an image based on analog voltage signals. The electronic device may also include optical calibration circuitry to generate digital-to-analog converter (DAC) data based on image data associated with the image and dither circuitry to reduce a bit-depth of the DAC data, generating dithered DAC data. Additionally, the electronic device may include a gamma generator having one or more DACs to generate the analog voltage signals based on the dithered DAC data, which may instruct the gamma generator to generate the analog voltage signals indicative of the image data.