知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.029 seconds)

    LIMITED BIT TOGGLING FOR DATA BUS INVERSION
    1.
    发明申请
    LIMITED BIT TOGGLING FOR DATA BUS INVERSION 有权

    公开(公告)号：US20250004530A1

    公开(公告)日：2025-01-02

    申请号：US18345940

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gregg Donley

    IPC: G06F9/30

    Abstract: The disclosed device includes multiple data elements each configured to send a bit of a bit sequence by toggling at most half of a number of bits from a previously sent bit sequence. The bit sequence can first be biased and then XORed with the previously sent bit sequence. Various other methods, systems, and computer-readable media are also disclosed.

    Combining write transactions of a large write
    2.
    发明授权
    Combining write transactions of a large write 有权

    公开(公告)号：US12210767B2

    公开(公告)日：2025-01-28

    申请号：US17032217

    申请日：2020-09-25

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Gregg Donley ,  Girish Balaiah Aswathaiya ,  Vydhyanathan Kalyanasundharam ,  Bryan Broussard

    IPC: G06F3/06

    Abstract: A system for combining write transactions of a large write includes a processor including at least a first die and a second die, and a link coupling the first die and the second die. When a link interface on one die transmits packets to the other die over the link, the link interface identifies, from a queue containing a plurality of write transactions, two or more write transactions in the queue that are candidates for combination based on one or more attributes of each write transaction. The link interface determines whether two or more candidate write transactions are combinable based on a set of conditions. When two or more candidate write transaction are combinable, the link interface combines the candidate write transactions into a single combined write transaction and transmits the combined write transaction. A link interface on the receiving die decodes the combined write transaction and iteratively regenerates the individual write transactions using control information in the combined write transaction.

    RUNNING AVERAGE CACHE HIT RATE
    5.
    发明申请
    RUNNING AVERAGE CACHE HIT RATE 有权

    公开(公告)号：US20250004943A1

    公开(公告)日：2025-01-02

    申请号：US18345974

    申请日：2023-06-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Edgar Munoz ,  Chintan S. Patel ,  Gregg Donley ,  Vydhyanathan Kalyanasundharam

    IPC: G06F12/0802

    Abstract: The disclosed device includes a first register that stores a cumulative delta value and a second register that stores an average cache hit rate. The device also includes a control circuit that calculates a cache hit rate and updates the cumulative delta value based on the cache hit rate and the average cache hit rate. The control circuit also updates the average cache hit rate based on the updated cumulative delta value, and can update a cache allocation policy based on the updated average cache hit rate. Various other methods, systems, and computer-readable media are also disclosed.

    Using age matrices for managing entries in sub-queues of a queue
    6.
    发明授权
    Using age matrices for managing entries in sub-queues of a queue 有权

    公开(公告)号：US10963402B1

    公开(公告)日：2021-03-30

    申请号：US16729377

    申请日：2019-12-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gregg Donley ,  Mark Silla

    IPC: G06F13/16 ,  G06F16/22

    Abstract: An electronic device includes a queue with multiple sub-queues arranged in a logical hierarchy from a lowest sub-queue to a highest sub-queue, each sub-queue including a separate subset of a set of entries of the queue, and a separate age matrix for each sub-queue. The electronic device also includes a controller that stores items in entries in the lowest sub-queue until the lowest sub-queue is full and then stores items in successively next higher sub-queues in the hierarchy. The controller also removes an item that is ready for removal from an entry in the lowest sub-queue. The controller then shifts items in sub-queues in the hierarchy to fill the vacancy in the lowest sub-queue. For the shifting, the controller uses an age matrix associated with each sub-queue to determine an oldest item in that sub-queue and then moves the oldest item to a next lower sub-queue in the hierarchy.

Patent Agency Ranking