公开(公告)号：US20220100813A1

公开(公告)日：2022-03-31

申请号：US17032314

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR ,  Arun Vaidyanathan ANANTHANARAYAN ,  Prasad NAGABHUSHANAMGARI

IPC: G06F17/16 ,  G06F13/28

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.

公开(公告)号：US20220100528A1

公开(公告)日：2022-03-31

申请号：US17032307

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR ,  Arun Vaidyanathan ANANTHANARAYAN ,  Prasad NAGABHUSHANAMGARI ,  Maxim V. KAZAKOV

IPC: G06F9/38 ,  G06F13/40 ,  G06F13/28

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.

公开(公告)号：US20220319096A1

公开(公告)日：2022-10-06

申请号：US17217339

申请日：2021-03-30

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Thomas Daniel PERRY ,  Gabor SINES ,  Mehdi SAEEDI ,  Allen H. RUSH

IPC: G06T15/06 ,  G06T17/20 ,  G06N3/02

Abstract: An apparatus includes a processor and a collision detection unit operatively coupled to the processor. The collision detection unit is configured to process, using a machine learning model, one or more parameters associated with a ray cast in virtual environment comprising an object. The machine learning model is configured to approximate a mesh representing the object. The collision detection unit is further configured to determine if the ray collides with the object based on processing the one or more parameters. In response to determining if the ray collides with the object, the collision detection unit is configured to generate collision data associated with the ray and the object.

公开(公告)号：US20220197973A1

公开(公告)日：2022-06-23

申请号：US17125457

申请日：2020-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh LAGUDU ,  Allen H. RUSH ,  Michael MANTOR

IPC: G06F17/16 ,  G06F9/30

Abstract: A processing system includes a first set and a second set of general-purpose registers (GPRs) and memory access circuitry that fetches nonzero values of a sparse matrix into consecutive slots in the first set. The memory access circuitry also fetches values of an expanded matrix into consecutive slots in the second set of GPRs. The expanded matrix is formed based on values of a vector and locations of the nonzero values in the sparse matrix. The processing system also includes a set of multipliers that concurrently perform multiplication of the nonzero values in slots of the first set of GPRs with the values of the vector in corresponding slots of the second set. Reduced sum circuitry accumulates results from the set of multipliers for rows of the sparse matrix.