公开(公告)号：US07934046B2

公开(公告)日：2011-04-26

申请号：US12166571

申请日：2008-07-02

Applicant: Adrian S Butter ,  Eric M Foster ,  Glenn D Gilda

Inventor： Adrian S Butter ,  Eric M Foster ,  Glenn D Gilda

IPC: G06F13/40

CPC classification number: G06F13/4031 ,  G06F12/1483

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract translation: 跨条块路由和访问表地址重映射功能在片上系统的交叉条中组合。 以这种方式，在段路由之前可能发生地址重映射。 每个主端口可能包含一个或多个访问表缓存寄存器。 高速缓存寄存器可以允许快速查找与每个主机相关联的一个或多个访问表条目，并且允许多个主机同时查找而不向接入表添加端口。 段标识符可以存储在高速缓存寄存器中，以指示如何将匹配请求路由到适当的从段。

公开(公告)号：US5454093A

公开(公告)日：1995-09-26

申请号：US660468

申请日：1991-02-25

Applicant: Jamee Abdulhafiz ,  Manuel J. Alvarez, II ,  Glenn D. Gilda

Inventor： Jamee Abdulhafiz ,  Manuel J. Alvarez, II ,  Glenn D. Gilda

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0859

Abstract: A computer system comprises a data processor, a main memory, a cache memory and an inpage buffer. The cache memory is coupled to the main memory to receive data therefrom and is coupled to the processor to transfer data thereto. The inpage buffer is coupled to the main memory to receive data therefrom, coupled to the cache memory to transfer data thereto, and coupled to the processor to transfer data thereto. Part of a line of data is originally transferred to the cache memory bypassing the inpage buffer to give the processor immediate access to the data which it needs. The remainder of the line of data is subsequently transferred to the inpage buffer, and then the processor is given access to the contents of the inpage buffer. The processor accesses the data in the cache memory with one set of clocks while the remainder of the line of data is transferred to the inpage buffer with another set of clocks. The two sets of clocks optimize the operation of tile processor and the main memory. Subsequently, the contents of the inpage buffer are transferred to the cache memory at the start of another inpage operation while the next line of data is fetched from the main memory.

Abstract translation: 计算机系统包括数据处理器，主存储器，高速缓存存储器和页内缓冲器。 高速缓存存储器耦合到主存储器以从其接收数据，并且耦合到处理器以向其传输数据。 入口缓冲器耦合到主存储器以从其接收数据，耦合到高速缓冲存储器以向其传送数据，并耦合到处理器以向其传输数据。 一行数据的一部分最初被转移到缓存中，绕过了inpage缓冲区，使处理器能够立即访问它所需要的数据。 数据行的其余部分随后被传送到入口缓冲器，然后处理器被访问内部缓冲器的内容。 处理器使用一组时钟访问高速缓冲存储器中的数据，而另一组时钟将数据行的其余部分传送到内部缓冲器。 两组时钟优化了瓷砖处理器和主存储器的操作。 随后，在从主存储器取出下一行数据的同时，在另一个页内操作开始时，将内页缓冲器的内容传送到高速缓冲存储器。

公开(公告)号：US4964737A

公开(公告)日：1990-10-23

申请号：US324929

申请日：1989-03-17

Applicant: Don L. Baker ,  Glenn D. Gilda ,  Terrence A. Quinn ,  Hussain Shaukatullah

Inventor： Don L. Baker ,  Glenn D. Gilda ,  Terrence A. Quinn ,  Hussain Shaukatullah

IPC: G01R31/26 ,  G01K1/14 ,  G01K13/00 ,  G01R31/28 ,  G01R31/30 ,  G06F11/22

CPC classification number: G01K13/00 ,  G01K1/14

Abstract: A portable thermocouple template is built to have one or more separate thermocouple beads fixedly attached at predetermined locations on a thin insulator sheet, with appropriate tape or the like for holding each thermocouple and its pair of connector wires in position on the sheet. The template is mountable between interconnected electronic components, such as on the pin side of a multichip module, in order to monitor the temperature of the adjacent components under actual operating conditions. After the test is completed and the temperature data is recorded and/or displayed on a data logger, the template and related assembly wires are removed and stored until such time as the template is needed for mounting again in order for additional thermal tests to be conducted.

公开(公告)号：US20100005213A1

公开(公告)日：2010-01-07

申请号：US12166571

申请日：2008-07-02

Applicant: Adrian S. Butter ,  Eric M. Foster ,  Glenn D. Gilda

Inventor： Adrian S. Butter ,  Eric M. Foster ,  Glenn D. Gilda

IPC: G06F13/14 ,  G06F13/36

CPC classification number: G06F13/4031 ,  G06F12/1483

Abstract: Cross-bar segment routing and access table address remapping functions are combined within a cross-bar of a system-on-a-chip. In this manner, address remapping may occur prior to segment routing. One or more access table caching registers may be included for each master port. The caching registers may allow for a rapid lookup of one or more access table entries associated with each master, as well as allow for the simultaneous lookup by multiple masters without adding ports to the access table. A segment identifier may be stored in the caching registers to indicate how to route a matching request to the appropriate slave segment.

Abstract translation: 跨条块路由和访问表地址重映射功能在片上系统的交叉条中组合。 以这种方式，在段路由之前可能发生地址重映射。 每个主端口可能包含一个或多个访问表缓存寄存器。 高速缓存寄存器可以允许快速查找与每个主机相关联的一个或多个访问表条目，并且允许多个主机同时查找而不向接入表添加端口。 段标识符可以存储在高速缓存寄存器中，以指示如何将匹配请求路由到适当的从段。

公开(公告)号：US06973528B2

公开(公告)日：2005-12-06

申请号：US10153041

申请日：2002-05-22

Applicant: Timothy C. Bronson ,  Glenn D. Gilda ,  John M. Sheplock ,  Phillip G. Williams

Inventor： Timothy C. Bronson ,  Glenn D. Gilda ,  John M. Sheplock ,  Phillip G. Williams

IPC: G06F12/08 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F12/0862 ,  G06F12/0875 ,  G06F13/4027 ,  G06F2212/303 ,  G06F2212/6022

Abstract: To prevent data performance impacts when dealing with target devices that can only transfer data for a limited number of bytes before disconnecting, the invention implements a short term data cache on the bridge. Using this feature, the bridge will cache additional data beyond a predetermined quantity of data following a disconnect with the requesting device. As such, the bridge may continue to prefetch additional data up to an amount specified by a prefetch read byte count and return the additional data should the requesting device request additional data resuming at the point of disconnect. However, the bridge will discard the additional data when at least one of the following occurs: a) the requesting device disconnects data transfer, and b) a further READ request that resumes at the point of disconnect is not received within a predetermined time.

Abstract translation: 为了防止在断开连接之前只能传输有限数量字节的数据的目标设备的数据性能影响，本发明实现了桥上的短期数据高速缓存。 使用此功能，桥接器将在与请求设备断开连接之后缓存超出预定数量的数据的附加数据。 因此，桥接器可以继续预取附加数据，直到预取读字节计数指定的量，并且如果请求设备在断开点请求附加数据恢复请求返回附加数据。 然而，当发生以下至少一个时，桥将丢弃附加数据：a）请求设备断开数据传输，并且b）在预定时间内没有接收到在断开点恢复的另一个READ请求。