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公开(公告)号：US20240282229A1
公开(公告)日：2024-08-22
申请号：US18653941
申请日：2024-05-02
发明人： Jun Young JUNG , Jin Woong JANG
CPC分类号： G09G3/007 , G09G3/32 , G09G2300/0814 , G09G2300/0842 , G09G2300/0871 , G09G2310/08 , G09G2340/0464
摘要： The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure may include an array of pixels, each pixel connected to a respective luminous element. The array of pixels comprises a first pixel comprising a first memory to configured to store image data to drive a first luminous element; and at least one pixel directly adjacent to the first pixel, each of the at least one pixel comparing a second memory electrically connected to the first memory, wherein the second memory is configured to receive the n-bit data from the first memory.
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公开(公告)号：US20240054928A1
公开(公告)日：2024-02-15
申请号：US18366257
申请日：2023-08-07
发明人： Ji Han KIM , Sung Ho HWANG , Ji Haeng LEE , Dae Young JUNG
IPC分类号： G09G3/00 , G09G3/3233
CPC分类号： G09G3/006 , G09G3/3233 , G09G2300/0819 , G09G2300/0842
摘要： A pixel driving circuit includes a memory unit storing data based on a first signal and a second signal, a driver connected to a luminous element and supplying electric power to the luminous element based on the data stored in the memory unit, and a test controller controlling entry into a test mode in which it is tested whether the pixel driving circuit is defective, wherein the test controller generates a test mode activation signal based on the first signal and the second signal.
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公开(公告)号：US11862071B2
公开(公告)日：2024-01-02
申请号：US17890737
申请日：2022-08-18
发明人： Jae Hoon Lee , Jun Young Jung
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2300/08 , G09G2310/0289 , G09G2310/08 , G09G2330/021
摘要： The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.
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公开(公告)号：US20230419889A1
公开(公告)日：2023-12-28
申请号：US18464429
申请日：2023-09-11
发明人： Jae Hoon LEE , Jin Woong JANG
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2300/0857 , G09G2310/08 , G09G2320/064 , G09G2330/021
摘要： The present invention is related to pixels and a display apparatus including: a display unit including a plurality of pixels; a signal control unit for generating a first voltage signal and a second voltage signal; a column driver connected to each of the pixels to transmit the first voltage signal to the pixel through a column line; and a row driver connected to each of the pixels to transmit the second voltage signal to the pixel through a row line, wherein the signal control unit generates the second voltage signal so that a voltage level of the second voltage signal rises to be higher than or equal to a predetermined level value during a non-emission period of the pixel.
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公开(公告)号：US11817041B2
公开(公告)日：2023-11-14
申请号：US17763429
申请日：2020-09-11
发明人： Jae Hoon Lee , Jin Woong Jang
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2300/0857 , G09G2310/08 , G09G2320/064 , G09G2330/021
摘要： The present invention is related to pixels and a display apparatus including: a display unit including a plurality of pixels; a signal control unit for generating a first voltage signal and a second voltage signal; a column driver connected to each of the pixels to transmit the first voltage signal to the pixel through a column line; and a row driver connected to each of the pixels to transmit the second voltage signal to the pixel through a row line, wherein the signal control unit generates the second voltage signal so that a voltage level of the second voltage signal rises to be higher than or equal to a predetermined level value during a non-emission period of the pixel.
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公开(公告)号：US11776462B2
公开(公告)日：2023-10-03
申请号：US17700611
申请日：2022-03-22
发明人： Ji Haeng Lee , Jin Woong Jang , Ji Han Kim , Dae Young Jung , Jong Gu Jeon , Do Kyung Kim
IPC分类号： G09G3/32
CPC分类号： G09G3/32 , G09G2310/08 , G09G2370/10
摘要： A display apparatus is capable of improving a dynamic false contour. The display apparatus may control to change an order of a plurality of pulses of which widths are modulated for an emission time set within one frame, or divide pulses corresponding to the most significant bit (MSB) and the second significant bit (MSB-1) of image data among the pulses into two or more sub-pulses, and output the sub-pulses.
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公开(公告)号：US20230005420A1
公开(公告)日：2023-01-05
申请号：US17942219
申请日：2022-09-12
发明人： Jae Hoon Lee , Jun Young Jung
IPC分类号： G09G3/32
摘要： The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.
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公开(公告)号：US20220293043A1
公开(公告)日：2022-09-15
申请号：US17763429
申请日：2020-09-11
发明人： Jae Hoon LEE , Jin Woong JANG
IPC分类号： G09G3/32
摘要： The present invention is related to pixels and a display apparatus including: a display unit including a plurality of pixels; a signal control unit for generating a first voltage signal and a second voltage signal; a column driver connected to each of the pixels to transmit the first voltage signal to the pixel through a column line; and a row driver connected to each of the pixels to transmit the second voltage signal to the pixel through a row line, wherein the signal control unit generates the second voltage signal so that a voltage level of the second voltage signal rises to be higher than or equal to a predetermined level value during a non-emission period of the pixel.
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公开(公告)号：US11170705B2
公开(公告)日：2021-11-09
申请号：US17155435
申请日：2021-01-22
发明人： Jae Hoon Lee , Jin Woong Jang
IPC分类号： G09G3/32
摘要： The present specification provides a pixel circuit miniaturized using a smaller number of transistors as compared with the related art. A 4T static random-access memory (SRAM) is used in an embedded pixel memory, and in order to prevent a voltage floating problem from occurring in a logic low state, a leakage current is designed to flow in one direction by adjusting a threshold voltage of a transistor. In addition, a pulse width modulation (PWM) control unit uses a smaller number of transistors as compared with the related art, and in order to prevent a voltage floating problem from occurring, a circuit capable of removing a floating voltage is provided.
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公开(公告)号：US12112699B2
公开(公告)日：2024-10-08
申请号：US18032461
申请日：2021-12-02
发明人： Jae Hoon Lee , Ji Han Kim
IPC分类号： G09G3/3233
CPC分类号： G09G3/3233 , G09G2310/0286 , G09G2310/08
摘要： The present specification discloses a pixel driving circuit having a reduced number of external contacts. A conventional digital driving pixel requires two contacts (Vcc, GND) related to power, a contact (row signal, column signal) for inputting two signals for digital driving, a contact (mode selection) for inputting a set value required for driving the pixel, and a contact (reset) for maintaining video data for one frame to implement a cycle function during PWM driving and for inputting a reset signal to clear previous video data before inputting new video data. However, the higher the number of contacts, the lower the efficiency of pick & place in the manufacturing process. Thus, in the present specification, a pixel driving circuit is proposed, which can be digitally driven even when the number of contacts is reduced through combination of a row signal and a column signal.
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