-
公开(公告)号：US12136562B2
公开(公告)日：2024-11-05
申请号：US18527269
申请日：2023-12-02
Applicant: Monolithic 3D Inc.
Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC: H01L23/48 , G11C8/16 , H01L21/683 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/00 , H01L23/367 , H01L25/00 , H01L25/065 , H10B20/20
Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.
-
公开(公告)号：US20240365544A1
公开(公告)日：2024-10-31
申请号：US18473896
申请日：2023-09-25
Applicant: Yangtze Memory Technologies Co., Ltd.
Inventor： Quanshan Lv , Jie Yuan , YaLi Song
Abstract: Examples of the present application provide a three-dimensional memory and manufacturing method thereof, and a memory system. The three-dimensional memory comprises: a stack structure comprising alternating stacked gate layers and dielectric layers; a plurality of channel columns penetrating the stack structure in a first direction and comprising: a barrier layer, a storage layer, a tunneling layer, and a channel layer arranged in sequence; and a plurality of isolation structures located between the dielectric layers and the tunneling layer in a second direction perpendicular to the first direction; wherein the isolation structures penetrating at least a portion of the storage layer in the second direction.
-
公开(公告)号：US12133379B2
公开(公告)日：2024-10-29
申请号：US17235577
申请日：2021-04-20
Applicant: SK hynix Inc.
Inventor： Nam Jae Lee
Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a channel structure including a first pillar part and a second pillar part extending from the first pillar part; a blocking insulating layer surrounding a sidewall of the first pillar part; a data storage layer disposed between the first pillar part and the blocking insulating layer; an upper select line overlapping with an end portion of the blocking insulating layer and an end portion of the data storage layer, which face in an extending direction of the second pillar part, the upper select line surrounding a sidewall of the second pillar part; and a tunnel insulating layer disposed between the first pillar part and the data storage layer, the tunnel insulating layer extending between the second pillar part and the upper select line.
-
公开(公告)号：US12125737B1
公开(公告)日：2024-10-22
申请号：US18736423
申请日：2024-06-06
Applicant: Monolithic 3D Inc.
Inventor： Zvi Or-Bach , Brian Cronquist , Deepak C. Sekar
IPC: H01L21/683 , G11C8/16 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/48 , H01L23/525 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/118 , H01L27/12 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L29/792 , H10B10/00 , H10B12/00 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/00 , H01L23/367 , H01L25/00 , H01L25/065 , H10B20/20
CPC classification number: H01L21/6835 , G11C8/16 , H01L21/743 , H01L21/76254 , H01L21/76898 , H01L21/8221 , H01L21/823828 , H01L21/84 , H01L23/481 , H01L23/5252 , H01L27/0207 , H01L27/0688 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/11807 , H01L27/11898 , H01L27/1203 , H01L29/4236 , H01L29/66272 , H01L29/66621 , H01L29/66825 , H01L29/66833 , H01L29/66901 , H01L29/78 , H01L29/7841 , H01L29/7843 , H01L29/7881 , H01L29/792 , H10B10/00 , H10B10/125 , H10B12/053 , H10B12/09 , H10B12/20 , H10B12/50 , H10B20/00 , H10B41/20 , H10B41/40 , H10B41/41 , H10B43/20 , H10B43/40 , H01L23/3677 , H01L24/13 , H01L24/16 , H01L24/45 , H01L24/48 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L27/1214 , H01L27/1266 , H01L2221/68368 , H01L2223/5442 , H01L2223/54426 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81005 , H01L2224/83894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00011 , H01L2924/01002 , H01L2924/01004 , H01L2924/01013 , H01L2924/01018 , H01L2924/01019 , H01L2924/01029 , H01L2924/01046 , H01L2924/01066 , H01L2924/01068 , H01L2924/01077 , H01L2924/01078 , H01L2924/01322 , H01L2924/10253 , H01L2924/10329 , H01L2924/12032 , H01L2924/12033 , H01L2924/12036 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/1579 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H10B12/05 , H10B20/20
Abstract: A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.
-
公开(公告)号：US12108598B2
公开(公告)日：2024-10-01
申请号：US17190739
申请日：2021-03-03
Applicant: Kioxia Corporation
Inventor： Kazuharu Yamabe
CPC classification number: H10B43/20 , H01L24/06 , H01L24/45 , H10B41/10 , H10B41/20 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: A semiconductor storage device includes a substrate, a plurality of first conductive layers arranged in a first direction intersecting with a surface of the substrate, a first semiconductor layer that extends in the first direction and faces the plurality of first conductive layers, a first gate insulating film that extends in the first direction and covers an outer peripheral surface of the first semiconductor layer, a first insulating layer that extends in the first direction and has an outer peripheral surface covered with the first semiconductor layer, and a second conductive layer that is farther from the substrate than the plurality of first conductive layers and is connected to one end in the first direction of the first semiconductor layer. The first semiconductor layer includes a first region facing the plurality of first conductive layers and a second region farther from the substrate than the first region. The second conductive layer is connected to an inner peripheral surface and an outer peripheral surface of the second region of the first semiconductor layer and is in contact with one end in the first direction of the first insulating layer.
-
86.发明公开
公开(公告)号：US20240321743A1
公开(公告)日：2024-09-26
申请号：US18593582
申请日：2024-03-01
Applicant: Kioxia Corporation
Inventor： Keisuke ISHIZUKA
CPC classification number: H01L23/5283 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/40
Abstract: A semiconductor storage device includes a first stacked body in which first conductive layers and first insulating layers are alternately stacked in a stacking direction, a second stacked body above the first stacked body and in which second conductive layers and second insulating layers are alternately stacked in the stacking direction, a contact that extends in the first and second stacked bodies in the stacking direction and is connected to a first conductive layer. The contact has a first portion that extends in the first stacked body and is connected at a lower end portion thereof to the first conductive layer, a second portion that extends in the second stacked body and is connected to an upper end portion of the first portion, the second portion having a cross-section at a lower end portion thereof that is smaller than a cross-section at the upper end portion of the first portion.
-
公开(公告)号：US12101930B2
公开(公告)日：2024-09-24
申请号：US17828417
申请日：2022-05-31
Applicant: SK hynix Inc.
Inventor： Jin Ho Kim , Kwang Hwi Park , Sang Hyun Sung , Sung Lae Oh , Chang Woon Choi
Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.
-
88.发明公开
公开(公告)号：US20240315039A1
公开(公告)日：2024-09-19
申请号：US18483331
申请日：2023-10-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Gyeongsik EOM , Inho KIM , Chankyu KIM , Jumi YUN , Young-Ho LEE , Dasom JUNG , Wongi HONG
IPC: H10B43/40 , H01L25/065 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00
CPC classification number: H10B43/40 , H01L25/0652 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/27 , H10B43/35 , H10B80/00 , H01L2225/06506
Abstract: A semiconductor device includes a cell area, wherein the cell area includes: a cell array area; a connection area; a gate stacking structure including a plurality of gate electrodes, wherein the gate stacking structure includes an upper structure and a lower structure; a plurality of channel structures that penetrates the gate stacking structure in the cell array area; and a plurality of gate contact portions that penetrates the gate stacking structure in the connection area, wherein a bottom gate electrode in the cell array area is in a bottom portion of the upper structure and is adjacent to a channel structure among the plurality of channel structures, and wherein a bottom insulating portion in the connection area is in the bottom portion of the upper structure and is adjacent to a gate contact portion among the plurality of gate contact portions.
-
公开(公告)号：US12082408B2
公开(公告)日：2024-09-03
申请号：US17481803
申请日：2021-09-22
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Yuancheng Yang , Wenxi Zhou , Zhiliang Xia , Wei Liu
IPC: H10B41/41 , G11C16/04 , G11C16/10 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
CPC classification number: H10B41/41 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L23/5283 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second peripheral circuit is between the bonding interface and the second semiconductor layer. The first semiconductor layer is between the polysilicon layer and the second semiconductor layer.
-
90.发明授权
公开(公告)号：US12080697B2
公开(公告)日：2024-09-03
申请号：US17525533
申请日：2021-11-12
Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Inventor： Shiqi Huang , Wei Liu , Bater Chelon , Siping Hu
IPC: H01L25/18 , H01L23/00 , H01L23/528 , H01L25/00 , H01L25/065 , H10B41/27 , H10B41/40 , H10B43/27 , H10B43/40
CPC classification number: H01L25/18 , H01L23/528 , H01L24/03 , H01L24/08 , H01L24/09 , H01L24/27 , H01L24/32 , H01L24/33 , H01L24/83 , H01L25/0657 , H01L25/50 , H10B41/27 , H10B41/40 , H10B43/27 , H10B43/40 , H01L2224/08112 , H01L2224/08146 , H01L2224/09181 , H01L2224/32147 , H01L2224/33181 , H01L2224/80895 , H01L2224/80896 , H01L2224/83895 , H01L2224/83896 , H01L2225/06541 , H01L2225/06565 , H01L2924/14511
Abstract: Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a plurality of first NAND memory strings and a plurality of first BLs. At least one of the first BLs may be conductively connected to a respective one of the first NAND memory strings. The first semiconductor structure also includes a plurality of first conductor layers, and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs and a plurality of first word line bonding contacts conductively connected to the first conductor layers. A second semiconductor structure includes a plurality of second NAND memory strings and a plurality of second BLs.
