-
公开(公告)号:US11972984B2
公开(公告)日:2024-04-30
申请号:US18088631
申请日:2022-12-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Ching-Ling Lin , Wen-An Liang , Chen-Ming Huang
IPC: H01L21/8234 , H01L21/764 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC classification number: H01L21/823481 , H01L21/764 , H01L21/823431 , H01L27/0886 , H01L29/0649 , H01L29/66545 , H01L29/66795 , H01L29/785
Abstract: A semiconductor device includes a fin-shaped structure on a substrate, a gate structure on the fin-shaped structure and an interlayer dielectric (ILD) layer around the gate structure, and a single diffusion break (SDB) structure in the ILD layer and the fin-shaped structure. Preferably, the SDB structure includes a bottom portion and a top portion on the bottom portion, in which the top portion and the bottom portion include different widths.
-
公开(公告)号:US11967622B2
公开(公告)日:2024-04-23
申请号:US17466205
申请日:2021-09-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Te-Chih Hsiung , Jyun-De Wu , Yi-Chen Wang , Yi-Chun Chang , Yuan-Tien Tu
IPC: H01L21/8234 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/088 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/78
CPC classification number: H01L29/41791 , H01L21/76804 , H01L21/76816 , H01L21/76831 , H01L21/823418 , H01L21/823431 , H01L21/823475 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H01L27/0886 , H01L29/401 , H01L29/4236 , H01L29/66795 , H01L29/7851
Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
-
公开(公告)号:US11967533B2
公开(公告)日:2024-04-23
申请号:US17355444
申请日:2021-06-23
Inventor: Shu-Uei Jang , Shu-Yuan Ku , Shih-Yao Lin
IPC: H01L29/78 , H01L21/311 , H01L21/3213 , H01L21/8234 , H01L27/088 , H01L29/66
CPC classification number: H01L21/823481 , H01L21/31116 , H01L21/32137 , H01L21/823431 , H01L27/0886 , H01L29/66545
Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate that both extend along a first direction. The method includes forming a dielectric fin extending along the first direction and is disposed between the first and second semiconductor fins. The method includes forming a dummy gate structure extending along a second direction and straddling the first and second semiconductor fins and the dielectric fin. The method includes removing a portion of the dummy gate structure over the dielectric fin to form a trench by performing an etching process that includes a plurality of stages. Each of the plurality of stages includes a combination of anisotropic etching and isotropic etching such that a variation of a distance between respective inner sidewalls of the trench along the second direction is within a threshold.
-
公开(公告)号:US20240128376A1
公开(公告)日:2024-04-18
申请号:US18395892
申请日:2023-12-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Chiang Chen , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC: H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/786
CPC classification number: H01L29/7851 , H01L21/823418 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/42392 , H01L29/4991 , H01L29/66795 , H01L29/78696
Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.
-
公开(公告)号:US20240128127A1
公开(公告)日:2024-04-18
申请号:US18398190
申请日:2023-12-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Chih-Kai Hsu , Ssu-l Fu , Chun-ya Chiu , Chi-Ting Wu , Chin-HUNG Chen , Yu-Hsiang Lin
IPC: H01L21/8234 , H01L27/088 , H01L29/06
CPC classification number: H01L21/823481 , H01L21/823431 , H01L27/0886 , H01L29/0649
Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
-
公开(公告)号:US11961900B2
公开(公告)日:2024-04-16
申请号:US17328389
申请日:2021-05-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuo-Cheng Chiang , Teng-Chun Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC: H01L29/66 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/161 , H01L29/165 , H01L29/78
CPC classification number: H01L29/6681 , H01L21/76229 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/161 , H01L29/66545 , H01L29/6656 , H01L29/165 , H01L29/7848 , H01L2029/7858
Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes device fins formed on a substrate; fill fins formed on the substrate and disposed among the device fins; and gate stacks formed on the device fins and the fill fins. The fill fins include a first dielectric material layer and a second dielectric material layer deposited on the first dielectric material layer. The first and second dielectric material layers are different from each other in composition.
-
公开(公告)号:US20240120236A1
公开(公告)日:2024-04-11
申请号:US18306716
申请日:2023-04-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-Jung Kuo , Po-Cheng Shih , Wan Chen Hsieh , Zhen-Cheng Wu , Chia-Hui Lin , Tze-Liang Lee
IPC: H01L21/762 , H01L21/02 , H01L21/8234 , H01L27/088
CPC classification number: H01L21/76224 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02304 , H01L21/02315 , H01L21/823481 , H01L27/0886
Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.
-
公开(公告)号:US11955552B2
公开(公告)日:2024-04-09
申请号:US17985991
申请日:2022-11-14
Inventor: Li-Zhen Yu , Huan-Chieh Su , Shih-Chuan Chiu , Lin-Yu Huang , Cheng-Chi Chuang , Chih-Hao Wang
IPC: H01L29/78 , H01L21/8238 , H01L27/088 , H01L29/417 , H01L29/49 , H01L29/66
CPC classification number: H01L29/785 , H01L21/823821 , H01L27/0886 , H01L29/41791 , H01L29/4975 , H01L29/66795 , H01L2029/7858
Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.
-
89.
公开(公告)号:US11955534B2
公开(公告)日:2024-04-09
申请号:US18077142
申请日:2022-12-07
Applicant: Intel Corporation
Inventor: Andrew W. Yeoh , Joseph Steigerwald , Jinhong Shin , Vinay Chikarmane , Christopher P. Auth
IPC: H01L29/66 , H01L21/02 , H01L21/033 , H01L21/28 , H01L21/285 , H01L21/308 , H01L21/311 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/02 , H01L27/088 , H01L27/092 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/167 , H01L29/417 , H01L29/51 , H01L29/78 , H01L49/02 , H10B10/00 , H01L23/00
CPC classification number: H01L29/66545 , H01L21/02532 , H01L21/02636 , H01L21/0337 , H01L21/28247 , H01L21/28518 , H01L21/28568 , H01L21/3086 , H01L21/31105 , H01L21/31144 , H01L21/76224 , H01L21/76232 , H01L21/76801 , H01L21/76802 , H01L21/76816 , H01L21/76834 , H01L21/76846 , H01L21/76849 , H01L21/76877 , H01L21/76897 , H01L21/823431 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823828 , H01L21/823842 , H01L21/823857 , H01L21/823871 , H01L21/823878 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53209 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L27/0207 , H01L27/0886 , H01L27/0922 , H01L27/0924 , H01L28/20 , H01L28/24 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/41791 , H01L29/516 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/66795 , H01L29/66818 , H01L29/7843 , H01L29/7845 , H01L29/7846 , H01L29/7848 , H01L29/785 , H01L29/7851 , H01L29/7854 , H10B10/12 , H01L21/02164 , H01L21/0217 , H01L21/0332 , H01L21/76883 , H01L21/76885 , H01L21/823437 , H01L21/823475 , H01L24/16 , H01L24/32 , H01L24/73 , H01L29/665 , H01L29/7842 , H01L29/7853 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204
Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
-
公开(公告)号:US11955369B2
公开(公告)日:2024-04-09
申请号:US17341640
申请日:2021-06-08
Applicant: International Business Machines Corporation
Inventor: Lan Yu , Chen Zhang , Huimei Zhou , Ruilong Xie
IPC: H01L29/66 , H01L21/74 , H01L21/8234 , H01L23/535 , H01L27/088
CPC classification number: H01L21/743 , H01L21/823475 , H01L21/823481 , H01L23/535 , H01L27/0886
Abstract: An approach for creating a buried local interconnect around a DDB (double diffusion break) to reduce parasitic capacitance on a semiconductor device is disclosed. The approach utilizes a metal, as the local interconnect, buried in a cavity around the DDB region of a semiconductor substrate. The metal is disposed by two dielectric layers and the substrate. The two dielectric layers are recessed beneath two gate spacers. The buried local interconnect is recessed into the cavity where the top surface of the interconnect is situated below the top surface of the surrounding S/D (source/drain) epi (epitaxy). The metal of the local interconnect can be made from W, Ru or Co.