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    Providing A Consolidated Sideband Communication Channel Between Devices
    81.
    发明申请
    Providing A Consolidated Sideband Communication Channel Between Devices 审中-公开
    在设备之间提供合并边带通信通道

    公开(公告)号：US20150089110A1

    公开(公告)日：2015-03-26

    申请号：US14557699

    申请日：2014-12-02

    Applicant: INTEL CORPORATION

    Inventor： David J. Harriman ,  Mahesh Wagh ,  Robert E. Gough ,  James E. Jaussi

    IPC: G06F13/40 ,  G06F1/32 ,  G06N99/00

    CPC classification number: G06F13/4027 ,  G06F1/3203 ,  G06F13/20 ,  G06F13/4295 ,  G06N99/005 ,  Y02D10/14 ,  Y02D10/151

    Abstract: In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有事务层和链路层的协议栈。 另外，第一物理（PHY）单元被耦合到协议栈，以经由物理链路提供处理器和耦合到处理器的设备之间的通信，其中第一PHY单元是低功率通信协议，并且包括第一物理 单位电路。 反过来，第二PHY单元被耦合到协议栈，以经由耦合在与物理链路分离的多核处理器和设备之间的边带信道来提供处理器和设备之间的通信，其中第二PHY单元包括第二物理单元 电路。 描述和要求保护其他实施例。

    Power Management For A System On A Chip (SoC)
    82.
    发明申请
    Power Management For A System On A Chip (SoC) 审中-公开
    片上系统电源管理（SoC）

    公开(公告)号：US20140365796A1

    公开(公告)日：2014-12-11

    申请号：US14464864

    申请日：2014-08-21

    Applicant: Intel Corporation

    Inventor： Woojong Han ,  Madhu Athreya ,  Ken Shoemaker ,  Arvind Mandhani ,  Mahesh Wagh ,  Ticky Thakkar

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

    Abstract: In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于在芯片上的系统（SoC）的第一子系统和功率管理单元（PMU）之间发送第一链路握手信号以请求进入第一子系统的省电状态的方法 在所述第一子系统和所述PMU之间发送第二链路握手信号以确认所述请求，以及将所述第一子系统置于省电状态，而不在所述PMU与所述第一子系统之间进一步发信号。 描述和要求保护其他实施例。

    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC)
    83.
    发明授权
    Providing a peripheral component interconnect (PCI)-compatible transaction level protocol for a system on a chip (SoC) 有权
    为芯片上的系统（SoC）提供外设组件互连（PCI）兼容的事务级协议，

    公开(公告)号：US08751722B2

    公开(公告)日：2014-06-10

    申请号：US13851337

    申请日：2013-03-27

    Applicant: Intel Corporation

    Inventor： Ken Shoemaker ,  Mahesh Wagh ,  Woojong Han ,  Madhu Athreya ,  Arvind Mandhani ,  Shreekant S. Thakkar

    IPC: G06F13/42 ,  G06F13/20 ,  G06F13/40 ,  G06F13/36

    CPC classification number: G06F13/404 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4027 ,  G06F13/4045

    Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括具有根据个人计算机（PC）协议和第二协议进行通信的适配器的装置。 耦合到适配器的第一接口是对从适配器的上游接收的事务执行地址转换和排序。 第一接口依次通过一个或多个物理单元耦合到异构资源，每个资源包括知识产权（IP）核心和垫片，其中垫片将实现用于IP核的PC协议的报头以使能 无需修改即可并入设备。 描述和要求保护其他实施例。

    Providing a load/store communication protocol with a low power physical unit
    84.
    发明授权
    Providing a load/store communication protocol with a low power physical unit 有权
    提供具有低功率物理单元的加载/存储通信协议

    公开(公告)号：US08737390B2

    公开(公告)日：2014-05-27

    申请号：US13870429

    申请日：2013-04-25

    Applicant: Intel Corporation

    Inventor： Sridharan Ranganathan ,  Mahesh Wagh ,  David J. Harriman

    IPC: H04L12/50 ,  H04Q11/00

    CPC classification number: G06F13/385 ,  G06F13/40 ,  H04L49/109

    Abstract: In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，可以使用融合协议栈来将通信从第一通信协议统一到第二通信协议，以提供跨物理互连的数据传输。 该堆叠可以并入包括用于包括交易和链路层的第一通信协议的协议栈的装置以及耦合到协议栈的物理（PHY）单元，以在装置和耦合到装置的设备之间通信 一个物理链接。 该PHY单元可以包括根据第二通信协议的物理单元电路。 描述和要求保护其他实施例。

    MULTICHIP PACKAGE LINK ERROR DETECTION
    87.
    发明申请
    MULTICHIP PACKAGE LINK ERROR DETECTION 有权

    公开(公告)号：US20220350698A1

    公开(公告)日：2022-11-03

    申请号：US17721290

    申请日：2022-04-14

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC: G06F11/10 ,  H04L1/00 ,  H04L1/20 ,  H04L9/40 ,  G06F13/16

    Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    System, apparatus and method for synchronizing multiple virtual link states over a package interconnect
    88.
    发明授权
    System, apparatus and method for synchronizing multiple virtual link states over a package interconnect 有权

    公开(公告)号：US11442876B2

    公开(公告)日：2022-09-13

    申请号：US16426361

    申请日：2019-05-30

    Applicant: Intel Corporation

    Inventor： Joon Teik Hor ,  Ting Lok Song ,  Mahesh Wagh ,  Su Wei Lim

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: In one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.

    Extending multichip package link off package
    89.
    发明授权
    Extending multichip package link off package 有权

    公开(公告)号：US11386033B2

    公开(公告)日：2022-07-12

    申请号：US17121534

    申请日：2020-12-14

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

    IPC: G06F13/40 ,  H01L25/065 ,  G06F13/42 ,  H01L23/538

    Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

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