公开(公告)号：US10026746B2

公开(公告)日：2018-07-17

申请号：US15604028

申请日：2017-05-24

Applicant: Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

Inventor： Jeong Gil Lee ,  Jee Yong Kim ,  Jung Hwan Lee ,  Dae Seok Byeon ,  Hyun Seok Lim

IPC: H01L27/115 ,  H01L27/1157 ,  H01L27/11524 ,  H01L23/535 ,  H01L29/06 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

公开(公告)号：US09524983B2

公开(公告)日：2016-12-20

申请号：US14988178

申请日：2016-01-05

Applicant: Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

Inventor： Byung-Jin Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

Abstract translation: 垂直存储器件包括衬底，栅极线，沟道，触点和接触间隔物。 栅极线在衬底上堆叠在彼此的顶部。 栅极线相对于衬底的顶表面在垂直方向上彼此间隔开。 栅极线包括相对于衬底的顶表面在平行方向上延伸的台阶部分。 通道沿垂直方向延伸穿过栅极线。 触点位于栅极线的台阶上。 接触垫片选择性地沿接触部分的侧壁形成。

公开(公告)号：US20160268302A1

公开(公告)日：2016-09-15

申请号：US14995845

申请日：2016-01-14

Applicant: Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

Inventor： Jung-Hwan Lee ,  Jee-Yong Kim ,  Dae-Seok Byeon

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42352 ,  H01L29/66833

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括交替绝缘层和栅电极的叠层。 半导体器件包括在堆叠中的通道凹槽中的沟道材料。 半导体器件在通道凹槽中包括在沟道材料上的电荷存储结构。 此外，半导体器件在沟道材料上包括栅极绝缘层。 栅极绝缘层将沟道材料的一部分切下。 还提供了形成半导体器件的相关方法。

公开(公告)号：US20160268264A1

公开(公告)日：2016-09-15

申请号：US15001877

申请日：2016-01-20

Applicant: Sung-Min Hwang ,  Jee-Yong Kim ,  Dae-Seok Byeon

Inventor： Sung-Min Hwang ,  Jee-Yong Kim ,  Dae-Seok Byeon

IPC: H01L27/115 ,  H01L23/535

CPC classification number: H01L27/115 ,  H01L27/11563 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

Abstract: A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.

Abstract translation: 垂直存储器件包括分别在基本上垂直于衬底的顶表面的垂直方向上彼此间隔开的多个电平的多个栅极电极，在衬底上沿垂直方向延伸并穿透 栅极电极和沿垂直方向延伸并与栅电极接触的多个接触插塞。 至少一个第二接触插塞形成在多个栅电极之间的第一栅电极上，并且在垂直方向上延伸。

公开(公告)号：US09406359B2

公开(公告)日：2016-08-02

申请号：US14683186

申请日：2015-04-10

Applicant: Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

Inventor： Hyun-Kook Park ,  Yeong-Taek Lee ,  Dae-Seok Byeon ,  Chi-Weon Yoon

IPC: G11C29/52 ,  G11C7/22 ,  G06F11/07 ,  G11C7/06 ,  G11C7/10 ,  G11C7/14 ,  G11C11/56 ,  G11C13/00 ,  G11C29/02 ,  G11C29/42 ,  G11C7/12

CPC classification number: G11C7/22 ,  G06F11/073 ,  G06F11/076 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1045 ,  G11C7/12 ,  G11C7/14 ,  G11C11/5642 ,  G11C13/004 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2013/0054 ,  G11C2213/72

Abstract: A method of operating a memory system including memory cells commonly connected to a first signal line in a memory cell array includes; dividing the memory cells according to cell regions, and independently performing read operations on memory cells disposed in each cell region using a read reference selected from a plurality of read references and respectively corresponding to each cell region.

Abstract translation: 一种操作存储器系统的方法，包括：存储单元阵列中包含共同连接到第一信号线的存储单元; 根据单元区域划分存储单元，并且使用从多个读取参考中选择并且分别对应于每个单元区域的读取参考，独立地对设置在每个单元区域中的存储单元执行读取操作。

公开(公告)号：US09230669B2

公开(公告)日：2016-01-05

申请号：US14154641

申请日：2014-01-14

Applicant: Bong-Kil Jung ,  Hyung-Gon Kim ,  Dae-Seok Byeon

Inventor： Bong-Kil Jung ,  Hyung-Gon Kim ,  Dae-Seok Byeon

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C29/04 ,  G06F11/10

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C16/24 ,  G11C29/04 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.

Abstract translation: 一种操作包括非易失性存储器件和控制非易失性存储器件的存储器控​​制器的存储器系统的方法，包括以包括多个扇区的页为单位从存储器单元阵列读取数据; 对页面的扇区的单位对读取的数据执行纠错解码; 选择至少一个目标扇区，其包括至少一个不可校正的误差并选择至少一个通过扇区，其中所述通过扇区的所有错误可通过所述纠错解码来校正; 禁止连接到所述至少一个通过扇区的位线的预充电，同时对连接到所述至少一个目标扇区的目标位线进行预充电; 以及对所述至少一个目标扇区中的数据执行读取重试操作。

公开(公告)号：US08923067B2

公开(公告)日：2014-12-30

申请号：US14050430

申请日：2013-10-10

Applicant: Dae-seok Byeon ,  Bo-geun Kim ,  Jae-woo Park

Inventor： Dae-seok Byeon ,  Bo-geun Kim ,  Jae-woo Park

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3404 ,  G11C16/3422

Abstract: A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system.

Abstract translation: 提供了一种用于操作存储器系统的方法。 该方法包括使用第一软读取电压读取非易失性存储器单元，由第一电压值表示第一软读取电压和第一硬读取电压之间的电压电平差; 以及使用与第一软读取电压成对的第二软读取电压读取非易失性存储单元，第二软读取电压和第一硬读取电压之间的电压电平差由第二电压值指示。 第二电压值不同于第一电压值。 此外，第一电压值和第二电压值之间的差异对应于针对存储器系统的非易失性存储器单元设置的多个阈值电压分布中的相邻阈值电压分布的不对称程度。

公开(公告)号：US20140198573A1

公开(公告)日：2014-07-17

申请号：US14154641

申请日：2014-01-14

Applicant: BONG-KIL JUNG ,  HYUNG-GON KIM ,  DAE-SEOK BYEON

Inventor： BONG-KIL JUNG ,  HYUNG-GON KIM ,  DAE-SEOK BYEON

IPC: G11C16/26 ,  G11C29/04 ,  G11C16/24

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C16/24 ,  G11C29/04 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method of operating a memory system including a non-volatile memory device and a memory controller controlling the non-volatile memory device, includes reading data from a memory cell array in a unit of a page which includes a plurality of sectors; performing error correction decoding on the read data in a unit of a sector of the page; selecting at least one target sector which includes at least one uncorrectable error and selecting at least one pass sector wherein all errors of the pass sector are correctable by the error correction decoding; inhibiting precharging of bit-lines connected to the at least one pass sector while precharging target bit lines connected to the at least one target sector; and performing a read retry operation for data in the at least one target sector.

Abstract translation: 一种操作包括非易失性存储器件和控制非易失性存储器件的存储器控​​制器的存储器系统的方法，包括以包括多个扇区的页为单位从存储器单元阵列读取数据; 对页面的扇区的单位对读取的数据执行纠错解码; 选择至少一个目标扇区，其包括至少一个不可校正的误差并选择至少一个通过扇区，其中所述通过扇区的所有错误可通过所述纠错解码来校正; 禁止连接到所述至少一个通过扇区的位线的预充电，同时对连接到所述至少一个目标扇区的目标位线进行预充电; 以及对所述至少一个目标扇区中的数据执行读取重试操作。

公开(公告)号：US08432741B2

公开(公告)日：2013-04-30

申请号：US13419732

申请日：2012-03-14

Applicant: Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

Inventor： Seung-Jae Lee ,  Dae-Seok Byeon ,  Hyun-Chul Ha

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C16/0408

Abstract: A nonvolatile memory device comprises a memory cell array, a row selection circuit and a voltage generator. The memory cell array comprises a first dummy memory cell, a second dummy memory cell, and a NAND string comprising a plurality of memory cells coupled in series between a string selection transistor and a ground selection transistor through the first dummy memory cell and the second dummy memory cell. During a read-out operation mode, a dummy read-out voltage is applied to a first dummy wordline coupled to the first dummy memory cell, and to a second dummy wordline coupled to the second dummy memory cell. The dummy read-out voltage has a lower magnitude than a read-out voltage applied to an unselected memory cell during the read-out operation mode.

Abstract translation: 非易失性存储器件包括存储单元阵列，行选择电路和电压发生器。 存储单元阵列包括第一虚拟存储单元，第二虚拟存储单元和NAND串，其包括通过第一虚拟存储单元和第二虚拟存储单元串联耦合在串选择晶体管和接地选择晶体管之间的多个存储单元 记忆单元 在读出操作模式期间，将虚拟读出电压施加到耦合到第一虚拟存储器单元的第一伪字线以及耦合到第二虚拟存储单元的第二虚拟字线。 在读出操作模式期间，虚拟读出电压具有比在未选择存储单元上施加的读出电压更低的量值。

公开(公告)号：US20120147669A1

公开(公告)日：2012-06-14

申请号：US13303819

申请日：2011-11-23

Applicant: Dae-Seok Byeon

Inventor： Dae-Seok Byeon

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/22

Abstract: A method for operating a non-volatile memory device includes programming a memory cell and not programming a flag cell during first to nth (n is a natural number equal to or greater than 1) program loops, and programming the memory cell and the flag cell during (n+1)th to mth (m is a natural number greater than n) program loops.

Abstract translation: 一种用于操作非易失性存储器件的方法包括编程存储器单元，并且在第一至第n（n是等于或大于1的自然数）程序循环期间不对标志单元进行编程，并且对存储器单元和标志单元进行编程 在第（n + 1）到第m（m是大于n的自然数）程序循环。