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公开(公告)号：US20230102304A1
公开(公告)日：2023-03-30
申请号：US17959229
申请日：2022-10-03
Applicant: Ciena Corporation
Inventor： Christine Latrasse , Alexandre Delisle-Simard , Michel Poulin , Ian Betty , Arash Khajooeizadeh , Michael Vitic
Abstract: An optical modulator includes a first Radio Frequency (RF) line and a second RF line; an optical waveguide along a length of the modulator with an input and an output; and a plurality of segments along the length including a first set of segments, a single RF line crossing, and a second set of segments, wherein the first set of segments and the second set of segments have an inversion of their respective orientation at the RF line crossing, and wherein the RF line crossing is located off center relative to the plurality of segments, wherein each of the first RF line and the second RF line extend along the length and cross one another at the RF line crossing.
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公开(公告)号：US20230095297A1
公开(公告)日：2023-03-30
申请号：US17709290
申请日：2022-03-30
Applicant: Ciena Corporation
Inventor： Cengiz Alaettinoglu , Amal Karboubi , Himanshu Shah , Muthurajah Sivabalan
IPC: H04L45/645 , H04L45/28 , H04L43/0811
Abstract: Systems and methods implemented in a network element in a Segment Routing network include, for a service having two or more candidate paths and responsive to a failure on a current candidate path of the two or more candidate paths, setting an eligibility flag for the current candidate path; and selecting another candidate path of the two or more candidate paths, for the service, based on their eligibility flag.
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公开(公告)号：US20230084020A1
公开(公告)日：2023-03-16
申请号：US17474105
申请日：2021-09-14
Applicant: Ciena Corporation
Inventor： Michel Poulin , Alexandre Delisle-Simard , Michael Vitic
Abstract: A first transmission line comprises a first pair of electrodes receiving an electrical drive comprising first and second drive signals, which are loaded by a first series of p-n junctions applying optical phase modulation to respective optical waves propagating over a first section of the first and second optical waveguide arms of an MZI. A second transmission line comprises a second pair of electrodes configured to receive the electrical drive after an electrical signal delay. The second pair of electrodes are loaded by a second series of p-n junctions applying optical phase modulation to the respective optical waves propagating over a second section of the first and second optical waveguide arms after propagation over the first section. An electrode extension structure provides the electrical drive to the second pair of electrodes, and comprises an unloaded transmission line portion imposing the electrical signal delay based on an optical signal delay.
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公开(公告)号：US11595302B2
公开(公告)日：2023-02-28
申请号：US17030205
申请日：2020-09-23
Applicant: Ciena Corporation
Inventor： Thor Odd Andres Ramsland , Himanshu Shah , Prabhakar Nagral , Dennis E. Hayes , Marc Holness
IPC: H04L12/741 , H04L12/755 , H04L12/715 , H04L12/733 , H04L45/00 , H04L45/021 , H04L45/745 , H04L45/02
Abstract: Systems and methods include obtaining a table having a plurality of addresses each having a plurality of attributes and classifications; responsive to a requirement to reduce a size of the table, reducing a number of the plurality of addresses based on one or more reduction approaches that use any of the plurality of attributes and classifications; and obtaining an output table having some or all of the plurality of addresses for a table receiver. The table can be obtained via control plane components including one or more of Interior Gateway Protocol (IGP) and Border Gateway Protocol (BGP). The requirement to reduce the size is based on a size of the table and a size of memory associated with the table receiver.
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公开(公告)号：US11595047B1
公开(公告)日：2023-02-28
申请号：US17685474
申请日：2022-03-03
Applicant: Ciena Corporation
Inventor： YoungJun Park , Sadok Aouini
Abstract: Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.
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Patent Agency Ranking
公开(公告)号：US20230057874A1
公开(公告)日：2023-02-23
申请号：US17493945
申请日：2021-10-05
Applicant: Ciena Corporation
Inventor： Ankur Jain , Suvendu Kumar Barik , John Wade Cherrington
IPC: H04L12/24
Abstract: Systems and methods include creating a graph of a network having i) vertices representing ports, and ii) edges representing possible connections between vertices; receiving a request for one or more paths in the network; traversing the graph to determine the one or more paths; responsive to encountering a non-local constraint in the graph, adding a traversal state based thereon; and responsive to satisfying the non-local constraint in the graph, removing the traversal state based thereon.
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公开(公告)号：US11588702B1
公开(公告)日：2023-02-21
申请号：US17574016
申请日：2022-01-12
Applicant: Ciena Corporation
Inventor： Christopher Stoll , Brett Sinclair , David Fortin , Blair E. P. Moxon , Christiane Louise Campbell , Sophy Pal , Brian Christopher Johnson , Hien Nguyen
IPC: G06F15/16 , H04L41/12 , H04L41/22 , G06F3/04815 , G06F3/0485 , G06F3/04842 , G06F3/04817
Abstract: Systems and methods include receiving data from a network that includes a plurality of network elements that operate at a plurality levels that include any of network layers and encapsulations; displaying any of the plurality of network elements as a three-dimensional icon on a network map; illustrating a plinth in the three-dimensional icon for each of the plurality of levels for each network element of the any of the plurality of network elements, wherein a plinth at each level indicates a corresponding network element participates in that level; and illustrating horizontal connectivity as links between any of the network elements via associated plinths.
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公开(公告)号：US11586059B2
公开(公告)日：2023-02-21
申请号：US17320345
申请日：2021-05-14
Applicant: Ciena Corporation
Inventor： Alexandre D. Simard , Yves Painchaud
Abstract: An optical modulator includes a rib; and a slab interconnected to both sides of the rib; wherein the rib is dimensioned relative to the slab to support guiding of a Transverse Magnetic (TM) mode with a main lobe that propagates orthogonal to the slab and with the main lobe substantially excluded from the slab. The rib guides wavelengths in an infrared range in the TM mode. A height of the rib, relative to the slab, is about half of a width of the rib, between the slab.
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公开(公告)号：US11582135B2
公开(公告)日：2023-02-14
申请号：US17068060
申请日：2020-10-12
Applicant: Ciena Corporation
Inventor： Ankur Jain , John Wade Cherrington
Abstract: Systems and methods for constrained path computation in networks with connectivity and resource availability rules build the necessary constraints directly into the routing graph so that all paths found are by construction satisfying of all the constraints. This is in contrast to the conventional approach of finding multiple paths and then applying the constraints. The present disclosure efficiently addresses the necessary constraints in the routing graph. Path Computation Engine (PCE) performance in terms of time to return acceptable paths to the user generically degrades as network scale (typically expressed through length and number of paths) increases. The present disclosure keeps the input graph small even though the graphs have expanded functionality to address constraints.
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公开(公告)号：US11579950B2
公开(公告)日：2023-02-14
申请号：US17015149
申请日：2020-09-09
Applicant: Ciena Corporation
Inventor： David Miedema , Bruno Doyle
IPC: G06F3/00 , G06F9/54 , G06F40/205 , G06F16/955
Abstract: A computing system includes a processing device and a memory device configured to store an Application Programming Interface (API) and computer software. The computer software has a plurality of software components configured to enable the processing device to utilize internal data for performing a plurality of functions. The API is configured to define interactions between the software components and is further configured to define access constraints with respect to the computing system. The access constraints are configured to restrict access by an end user associated with the computing system with respect to the internal data and software components. Also, the computer software is configured to adjust the access constraints of the API.
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