IC with saw-less RF front-end
    81.
    发明申请
    IC with saw-less RF front-end 审中-公开
    IC带无锯频RF前端

    公开(公告)号:US20080299935A1

    公开(公告)日:2008-12-04

    申请号:US11888784

    申请日:2007-08-02

    IPC分类号: H04B1/26

    CPC分类号: H04B1/525

    摘要: An IC includes an RF front end, a down conversion module, an up conversion module, and a local oscillation generating module. The RF front end includes a receive section, a transmit section, and an interference reduction module. The receive section receives an inbound RF signal within a receive frequency band and the transmit section transmits an outbound RF signal within a transmit frequency band. The interference reduction module is coupled to at least one of the receive section and the transmit section and facilitates at least one of: attenuating energy of the outbound RF signal within the receive frequency band based on a transmit local oscillation or a receive local oscillation; and attenuating energy of the inbound RF signal within the transmit frequency band based on the transmit local oscillation or the receive local oscillation.

    摘要翻译: IC包括RF前端,下变频模块,上变频模块和本地振荡产生模块。 RF前端包括接收部分,发送部分和干扰减少模块。 接收部分在接收频带内接收入站RF信号,并且发送部分发送发射频带内的出站RF信号。 所述干扰减少模块耦合到所述接收部分和所述发射部分中的至少一个,并且促进以下至少一个:基于发射本地振荡或接收本地振荡来衰减所述接收频带内的出站RF信号的能量; 并且基于发射本地振荡或接收本地振荡来衰减发射频带内的入站RF信号的能量。

    Merged high pass filtering and down-converting mixer circuit
    82.
    发明申请
    Merged high pass filtering and down-converting mixer circuit 有权
    合并高通滤波和下变频混频电路

    公开(公告)号:US20080287087A1

    公开(公告)日:2008-11-20

    申请号:US11804535

    申请日:2007-05-17

    IPC分类号: H04B1/26

    摘要: According to one exemplary embodiment, a mixer circuit comprises first and second switching branches driven by a local oscillator and an input radio frequency (RF) signal. The mixer circuit further comprises at least one capacitor coupled between the first and second switching branches for high-pass filtering of a down-converted output signal of the mixer circuit. In one embodiment, each switching branch comprises a respective mixer transistor, for example, a field effect transistor (FET). In one embodiment, the mixer circuit includes an inductor to reduce or eliminate the effects of parasitic capacitors at a resonance frequency selected to approximately match a desired RF signal frequency. In one embodiment, an inductor at resonance with parasitic capacitors produces a band pass filter for an input RF signal.

    摘要翻译: 根据一个示例性实施例,混频器电路包括由本地振荡器和输入射频(RF)信号驱动的第一和第二开关分支。 混频器电路还包括耦合在第一和第二开关分支之间的至少一个电容器,用于对混频器电路的下变频输出信号进行高通滤波。 在一个实施例中,每个开关支路包括相应的混频器晶体管,例如场效应晶体管(FET)。 在一个实施例中,混频器电路包括电感器,以减少或消除在被选择为近似匹配期望的RF信号频率的谐振频率处的寄生电容器的影响。 在一个实施例中,与寄生电容共振的电感器产生用于输入RF信号的带通滤波器。

    High frequency divider circuits and methods

    公开(公告)号:US20070024330A1

    公开(公告)日:2007-02-01

    申请号:US11142705

    申请日:2005-06-01

    IPC分类号: H03K23/00

    摘要: Embodiments of the present invention include circuits and methods for dividing high frequency signals. In one embodiment the present invention includes a divider circuit comprising a differential circuit having first and second inputs to receive a first differential signal, a first frequency control input and first and second differential outputs, wherein the differential circuit has a first bias current. The divider circuit further includes a cross-coupled circuit having outputs coupled to the differential circuit outputs and a second frequency control input, wherein the cross-coupled circuit has a second bias current. Embodiments of the present invention may include circuits for controlling the relationship between bias currents and circuit parameters that vary with process or temperature or both.

    Divider circuits and methods using in-phase and quadrature signals
    84.
    发明申请
    Divider circuits and methods using in-phase and quadrature signals 有权
    分频电路和使用同相和正交信号的方法

    公开(公告)号:US20070024329A1

    公开(公告)日:2007-02-01

    申请号:US11142575

    申请日:2005-06-01

    IPC分类号: H03K23/00

    CPC分类号: H03K23/44

    摘要: Embodiments of the present invention include circuits and methods for dividing signals. In one embodiment the present invention includes a divider circuit comprising at least one first divider input receiving an in-phase (I+) signal, at least one second divider input receiving a complement of the in-phase (I−) signal, at least one third divider input receiving a quadrature (Q+) signal, and at least one fourth divider input receiving a complement of the quadrature (Q−) signal. In one embodiment, the lock range of a divider is improved by providing a first bias current greater than a second bias current.

    摘要翻译: 本发明的实施例包括用于分割信号的电路和方法。 在一个实施例中,本发明包括分频器电路,其包括接收同相(I +)信号的至少一个第一分频器输入,接收同相(I-)信号的补码的至少一个第二分频器输入,至少一个 接收正交(Q +)信号的第三分频器输入端和接收正交(Q-)信号的补码的至少一个第四分频器输入端。 在一个实施例中,通过提供大于第二偏置电流的第一偏置电流来改善分频器的锁定范围。