公开(公告)号：US20120329231A1

公开(公告)日：2012-12-27

申请号：US13603100

申请日：2012-09-04

Applicant: Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

Inventor： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

IPC: H01L21/762 ,  H01L21/336

CPC classification number: H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

Abstract translation: 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

公开(公告)号：US20120302038A1

公开(公告)日：2012-11-29

申请号：US13339404

申请日：2011-12-29

Applicant: Chunsheng ZHENG ,  Wenguang ZHANG ,  Qiang XU ,  Yuwen CHEN

Inventor： Chunsheng ZHENG ,  Wenguang ZHANG ,  Qiang XU ,  Yuwen CHEN

IPC: H01L21/302

CPC classification number: H01L21/76237 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

Abstract: A method for preparing a shallow trench isolation structure with the stress of its isolation oxide being tuned by ion implantation comprises: step a: forming a protective layer on a semiconductor substrate; step b: forming trenches for isolating PMOS active regions and NMOS active regions on the semiconductor substrate and the protective layer; step c: forming a filling material layer in the trenches, so that the trenches are fully filled with the filling material layer to form shallow trench isolation structures. The advantageous is that, as for a device where a HARP process is applied to its shallow trench isolation, the stress in the STI can be tuned so as to be changed from tensile stress into compressive stress by performing ion implantation to the STI around the PMOS, therefore the stress state of the PMOS channel region may be changed and the performance thereof is improved.

Abstract translation: 通过离子注入来调节其隔离氧化物的应力的浅沟槽隔离结构的制备方法包括：步骤a：在半导体衬底上形成保护层; 步骤b：形成用于隔离半导体衬底和保护层上的PMOS有源区和NMOS有源区的沟槽; 步骤c：在沟槽中形成填充材料层，使得沟槽被填充材料层完全填充以形成浅沟槽隔离结构。 有利的是，对于将HARP工艺应用于其浅沟槽隔离的器件，可以调节STI中的应力，以便通过对PMOS周围的STI进行离子注入，将其从拉伸应力变为压应力 因此，可以改变PMOS沟道区的应力状态并提高其性能。

公开(公告)号：US08298011B2

公开(公告)日：2012-10-30

申请号：US13080794

申请日：2011-04-06

Applicant: Yasushi Tateshita

Inventor： Yasushi Tateshita

IPC: H01L21/3205

CPC classification number: H01L29/7846 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/28194 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method for making a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.

Abstract translation: 一种制造半导体器件的方法，包括：以掩模在半导体衬底中的状态形成的元件隔离区域，使得半导体衬底的元件形成区域插入在元件隔离区域之间; 栅电极，形成在元件形成区上，栅极绝缘膜介于栅电极和元件形成区之间，栅电极形成为跨越元件形成区; 以及形成在栅电极两侧的元件形成区域中的源极 - 漏极区域，其中由栅极电极下方的元件形成区域形成的沟道区域形成为从元件隔离区域突出，并且源极 - 漏极 区域形成在比元件隔离区域的表面更深的位置。

公开(公告)号：US08293614B2

公开(公告)日：2012-10-23

申请号：US13333118

申请日：2011-12-21

Applicant: Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Verma Purakh

Inventor： Sanford Chu ,  Yisuo Li ,  Guowei Zhang ,  Verma Purakh

IPC: H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7846

Abstract: An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.

Abstract translation: LDMOS器件包括具有表面的衬底和覆盖该表面的栅电极，并且在栅电极下方的衬底中限定沟道区。 漏极区域与沟道区域隔开隔离区域。 隔离区域包括高拉伸应力的区域，并且被配置为在靠近漏极区域的基板中引起局部应力。 隔离区域中的高拉伸应力的区域可以由高应力氧化硅或高应力氮化硅形成。 在优选实施例中，隔离区是形成在栅极电极和漏极区域中间的衬底中的浅沟槽隔离区。

公开(公告)号：US20120256276A1

公开(公告)日：2012-10-11

申请号：US13082387

申请日：2011-04-07

Applicant: Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

Inventor： Guang-Yaw Hwang ,  Chun-Hsien Lin ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Zhi-Cheng Lee ,  Shao-Hua Hsu ,  Yi-Wen Chen ,  Cheng-Guo Chen ,  Jung-Tsung Tseng ,  Chien-Ting Lin ,  Tong-Jyun Huang ,  Jie-Ning Yang ,  Tsung-Lung Tsai ,  Po-Jui Liao ,  Chien-Ming Lai ,  Ying-Tsung Chen ,  Cheng-Yu Ma ,  Wen-Han Hung ,  Che-Hua Hsu

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract translation: 提供一种制造金属栅极的方法。 该方法包括提供基板。 然后，在基板上形成栅极电介质层。 在栅极电介质层上形成具有功函数金属层的多层堆叠结构。 在多层堆叠结构的至少一层上进行O2气氛处理。 在多层堆叠结构上形成导电层。

公开(公告)号：US20120228707A1

公开(公告)日：2012-09-13

申请号：US13263222

申请日：2011-08-25

Applicant: Jing Wang ,  Jun Xu ,  Lei Guo

Inventor： Jing Wang ,  Jun Xu ,  Lei Guo

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L29/78684 ,  H01L29/7846

Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

Abstract translation: 提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及延伸到硅衬底中并填充有绝缘电介质材料以在沟道区域中产生应变的多个浅沟槽隔离结构。 此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

公开(公告)号：US08232180B2

公开(公告)日：2012-07-31

申请号：US12886119

申请日：2010-09-20

Applicant: Naoyoshi Tamura

Inventor： Naoyoshi Tamura

IPC: H01L21/762

CPC classification number: H01L21/823807 ,  H01L21/76224 ,  H01L21/823878 ,  H01L29/7846

Abstract: The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between both active regions, and a second element isolation structure formed in the region other than the first element isolation structure.

Abstract translation: NMOS晶体管的有源区域和PMOS晶体管的有源区域被STI元件隔离结构划分。 STI元件隔离结构由形成为包括两个有源区之间的间隔的第一元件隔离结构和形成在第一元件隔离结构之外的区域中的第二元件隔离结构构成。

公开(公告)号：US08232178B2

公开(公告)日：2012-07-31

申请号：US13201371

申请日：2011-01-27

Applicant: Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L21/76

CPC classification number: H01L29/045 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

Abstract: A method for forming a semiconductor device with stressed trench isolation is provided, comprising: providing a silicon substrate (S11); forming at least two first trenches in parallel on the silicon substrate and forming a first dielectric layer which is under tensile stress in the first trenches (S12); forming at least two second trenches, which have an extension direction perpendicular to that of the first trenches, in parallel on the silicon substrate, and forming a second dielectric layer in the second trenches (S13); and after forming the first trenches, forming a gate stack on a part of the silicon substrate between two adjacent first trenches, wherein the channel length direction under the gate stack is parallel to the extension direction of the first trenches (S14). The present invention supply tensile stress in the channel width direction of a MOS transistor, so as to improve performance of PMOS and/or NMOS transistors.

Abstract translation: 提供一种用于形成具有应力沟槽隔离的半导体器件的方法，包括：提供硅衬底（S11）; 在所述硅衬底上平行地形成至少两个第一沟槽，并形成在所述第一沟槽中处于拉伸应力的第一介电层（S12）; 在所述硅衬底上形成平行于所述硅衬底的至少两个具有与所述第一沟槽的延伸方向垂直的第二沟槽，以及在所述第二沟槽中形成第二电介质层（S13）。 并且在形成第一沟槽之后，在两个相邻的第一沟槽之间的硅衬底的一部分上形成栅极叠层，其中栅叠层下方的沟道长度方向平行于第一沟槽的延伸方向（S14）。 本发明在MOS晶体管的沟道宽度方向上提供拉伸应力，以提高PMOS和/或NMOS晶体管的性能。

公开(公告)号：US08216913B2

公开(公告)日：2012-07-10

申请号：US12343780

申请日：2008-12-24

Applicant: Hiroaki Niimi ,  Elisabeth Marley

Inventor： Hiroaki Niimi ,  Elisabeth Marley

IPC: H01L21/76

CPC classification number: H01L21/76237 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/7846

Abstract: Adding nitrogen to the Si—SiO2 interface at STI sidewalls increases carrier mobility in MOS transistors, but control of the amount of nitrogen has been problematic due to loss of the nitrogen during liner oxide growth. This invention discloses a method of forming STI regions which have a controllable layer of nitrogen atoms at the STI sidewall interface. Nitridation is performed on the STI sidewalls by exposure to a nitrogen-containing plasma, by exposure to NH3 gas at high temperatures, or by deposition of a nitrogen-containing thin film. Nitrogen is maintained at a level of 1.0·1015 to 3.0·1015 atoms/cm2, preferably 2.0·1015 to 2.4·1015 atoms/cm2, at the interface after growth of a liner oxide by adding nitrogen-containing gases to an oxidation ambient. The density of nitrogen is adjusted to maximize stress in a transistor adjacent to the STI regions. An IC fabricated according to the inventive method is also disclosed.

Abstract translation: 在STI侧壁上向Si-SiO 2界面添加氮增加了MOS晶体管中的载流子迁移率，但是由于在衬里氧化物生长期间氮的损失，氮的量的控制是有问题的。 本发明公开了一种形成在STI侧壁界面具有可控氮原子层的STI区的方法。 通过暴露于含氮等离子体，通过在高温下暴露于NH 3气体，或通过沉积含氮薄膜，在STI侧壁上进行氮化。 在通过向氧化环境中加入含氮气体的衬垫氧化物生长之后的界面处，氮保持在1.0×10 15至3.0×10 15原子/ cm 2，优选2.0×10 15至2.4×10 15原子/ cm 2的水平。 调节氮的密度以使与STI区相邻的晶体管中的应力最大化。 还公开了根据本发明方法制造的IC。

公开(公告)号：US20120126244A1

公开(公告)日：2012-05-24

申请号：US13119004

申请日：2011-01-27

Applicant: Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

Inventor： Huicai Zhong ,  Haizhou Yin ,  Qingqing Liang ,  Huilong Zhu

IPC: H01L29/12 ,  H01L29/16 ,  H01L21/761 ,  H01L27/04 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224

Abstract: The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.

Abstract translation: 本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度 。 本发明减少了对于半导体器件性能的影响。