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公开(公告)号：US20240290656A1
公开(公告)日：2024-08-29
申请号：US18655989
申请日：2024-05-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Da Cheng , Wen-Hsiung Lu , Chin Wei Kang , Yung-Han Chuang , Lung-Kai Mao , Yung-Sheng Lin
IPC: H01L21/768 , H01L23/00
CPC classification number: H01L21/76885 , H01L21/76802 , H01L21/76852 , H01L21/76871 , H01L24/05 , H01L24/13 , H01L24/32 , H01L2224/0231 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022
Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
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公开(公告)号：US20240274558A1
公开(公告)日：2024-08-15
申请号：US18641836
申请日：2024-04-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsiang-Ku Shen , Dian-Hau Chen
IPC: H01L23/00
CPC classification number: H01L24/05 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02333 , H01L2224/0235 , H01L2224/02381 , H01L2224/0239 , H01L2224/0401 , H01L2224/05647 , H01L2224/10126 , H01L2224/13024 , H01L2224/1357
Abstract: A semiconductor structure includes a first dielectric layer over a metal line and a redistribution layer (RDL) over the first dielectric layer. The RDL is electrically connected to the metal line. The RDL has a curved top surface and a footing feature, where the footing feature extends laterally from a side surface of the RDL. A second dielectric layer is disposed over the RDL, where the second dielectric layer also has a curved top surface.
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公开(公告)号：US20240222194A1
公开(公告)日：2024-07-04
申请号：US18604691
申请日：2024-03-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Da Cheng , Tzy-Kuang Lee , Song-Bor Lee , Wen-Hsiung Lu , Po-Hao Tsai , Wen-Che Chang
IPC: H01L21/768 , H01L23/00
CPC classification number: H01L21/76885 , H01L21/76802 , H01L21/76852 , H01L21/76871 , H01L24/05 , H01L24/13 , H01L24/32 , H01L2224/0231 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0391 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022
Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.
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公开(公告)号：US11967549B2
公开(公告)日：2024-04-23
申请号：US17509046
申请日：2021-10-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung Ho Park , Jong Youn Kim , Min Jun Bae
IPC: H01L21/00 , H01L23/00 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/538 , H01L21/48 , H01L21/56 , H01L23/42
CPC classification number: H01L23/49838 , H01L23/3128 , H01L23/367 , H01L23/49816 , H01L23/49822 , H01L23/5383 , H01L23/5386 , H01L24/08 , H01L21/4853 , H01L21/4857 , H01L21/568 , H01L23/42 , H01L2224/02331 , H01L2224/0235 , H01L2224/02371 , H01L2224/024 , H01L2224/08235
Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposed to each other, and including an insulation member, a plurality of redistribution layers on different levels in the insulation member, and a redistribution via having a shape narrowing from the second surface toward the first surface in a first direction; a plurality of UBM layers, each including a UBM pad on the first surface of the redistribution substrate, and a UBM via having a shape narrowing in a second direction, opposite to the first direction; and at least one semiconductor chip on the second surface of the redistribution substrate, and having a plurality of contact pads electrically connected to the redistribution layer adjacent to the second surface among the plurality of redistribution layers.
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公开(公告)号：US20240047395A1
公开(公告)日：2024-02-08
申请号：US17818003
申请日：2022-08-08
Applicant: NANYA TECHNOLOGY CORPORATION
Inventor： Sheng-Fu HUANG , Shing-Yih SHIH
IPC: H01L23/00 , H01L25/065
CPC classification number: H01L24/08 , H01L25/0657 , H01L24/05 , H01L2225/06524 , H01L2225/06541 , H01L2924/3511 , H01L2224/08145 , H01L2224/05687 , H01L2224/0236 , H01L2224/0235 , H01L2224/08146 , H01L2224/02371 , H01L2224/02373 , H01L2224/02381 , H01L2224/024
Abstract: A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
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公开(公告)号：US20230352351A1
公开(公告)日：2023-11-02
申请号：US17731145
申请日：2022-04-27
Inventor： PEI-LUM MA , KUN DA JHONG , HSUEH-HAN LU , KUN-EI CHEN , CHEN-CHIEH CHIANG , LING-SUNG WANG
CPC classification number: H01L22/32 , H01L24/02 , H01L22/12 , H01L22/14 , H01L24/05 , H01L24/03 , H01L24/06 , H01L28/10 , H01L2224/0235 , H01L2224/03614 , H01L2224/03622 , H01L2224/0363 , H01L2224/0392 , H01L2224/0391 , H01L2224/05013 , H01L2224/05015 , H01L2224/05012 , H01L2224/06515 , H01L2224/0603 , H01L2224/05073 , H01L2224/05564 , H01L2224/05573 , H01L2224/05686
Abstract: A semiconductor structure is provided. The semiconductor structure includes an interconnection structure, a first conductive pad, a second conductive pad, a conductive material and a conductive coil. The first and second conductive pads are disposed over and electrically connected to the interconnection structure individually. The conductive material is electrically isolated from the interconnection structure, wherein bottom surfaces of the conductive material, the first conductive pad and the second conductive pad are substantially aligned. The conductive coil is disposed in the interconnection structure and overlapped by the conductive material. A manufacturing method of a semiconductor structure is also provided.
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公开(公告)号：US20230238359A1
公开(公告)日：2023-07-27
申请号：US17897181
申请日：2022-08-28
Applicant: Samsung Elctronics Co., Ltd.
Inventor： KWANG-SOO KIM
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L23/528
CPC classification number: H01L25/0657 , H01L24/73 , H01L24/48 , H01L24/32 , H01L23/49838 , H01L23/49816 , H01L24/06 , H01L23/5283 , H01L23/5286 , H01L2924/1438 , H01L2924/1436 , H01L2924/1431 , H01L2225/0651 , H01L2225/06524 , H01L2225/06562 , H01L2224/48227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73265 , H01L2224/73215 , H01L2224/06131 , H01L2224/024 , H01L2224/0235 , H01L2224/02373 , H01L2224/02375 , H01L2224/02381
Abstract: Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.
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公开(公告)号：US11658143B2
公开(公告)日：2023-05-23
申请号：US16723066
申请日：2019-12-20
Inventor： Sheng-Yu Wu , Tin-Hao Kuo , Chen-Shien Chen
IPC: H01L23/498 , H01L23/00 , H05K1/11 , H01L25/10 , H01L29/66 , H01L25/065 , H01L23/528 , H01L23/31
CPC classification number: H01L24/17 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/49894 , H01L23/528 , H01L24/02 , H01L24/09 , H01L24/14 , H01L24/16 , H01L24/33 , H01L24/81 , H01L25/0657 , H01L25/105 , H01L29/66 , H05K1/111 , H01L23/3192 , H01L24/05 , H01L24/13 , H01L2224/0235 , H01L2224/02375 , H01L2224/0401 , H01L2224/05073 , H01L2224/05166 , H01L2224/05548 , H01L2224/05572 , H01L2224/05647 , H01L2224/1308 , H01L2224/13022 , H01L2224/13082 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14133 , H01L2224/16013 , H01L2224/16145 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/3003 , H01L2224/81191 , H01L2224/81192 , H01L2224/81385 , H01L2224/81815 , H01L2225/06513 , H01L2225/1047 , H01L2225/1058 , H01L2924/3512 , H01L2924/35121 , H01L2924/3841 , H05K2201/09727 , H05K2201/10674 , Y02P70/50 , H01L2224/05647 , H01L2924/00014 , H01L2224/05166 , H01L2924/00014 , H01L2224/05073 , H01L2224/05647 , H01L2224/05166 , H01L2224/13147 , H01L2924/00014 , H01L2224/13155 , H01L2224/13144 , H01L2924/00014 , H01L2224/13164 , H01L2924/00014 , H01L2924/00014 , H01L2224/05572 , H01L2924/00014 , H01L2224/13111 , H01L2924/01047 , H01L2224/13111 , H01L2924/01029 , H01L2224/13111 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2224/0235 , H01L2924/00012 , H01L2224/02375
Abstract: A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.
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公开(公告)号：US20180337066A1
公开(公告)日：2018-11-22
申请号：US16048989
申请日：2018-07-30
Inventor： Hung-Jen Lin , Tsung-Ding Wang , Chien-Hsun Lee
IPC: H01L21/56 , H01L23/31 , H01L23/00 , H01L23/525
CPC classification number: H01L21/566 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/525 , H01L23/564 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0235 , H01L2224/02375 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0347 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05548 , H01L2224/05552 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/1191 , H01L2224/13005 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/181 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2924/206 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2924/00
Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
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公开(公告)号：US20180219031A1
公开(公告)日：2018-08-02
申请号：US14897763
申请日：2015-10-28
Inventor： Peng DU
IPC: H01L27/12 , G02F1/1345 , G02F1/1362
CPC classification number: H01L27/1255 , G02F1/1345 , G02F1/136286 , G02F1/1368 , G02F2001/13629 , H01L24/02 , H01L27/124 , H01L2224/02331 , H01L2224/0235 , H01L2224/02375 , H01L2224/02379
Abstract: Provided is a fan-out structure and an electronic device. In the fan-out structure, first fan-out lines are located on a different metal layer from second fan-out lines, and vertical projections of the first fan-out lines on the second metal layer partially overlap with the second fan-out lines, so as to form capacitance between the first fan-out lines and the second fan-out lines. The display effects of a display panel can be remarkably improved while a frame of the electronic device is favorably narrowed.
