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公开(公告)号：US20210067714A1
公开(公告)日：2021-03-04
申请号：US16555796
申请日：2019-08-29
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara , Eiichi Funatsu
Abstract: A photodiode array circuit includes a plurality of photodiode circuits, binning circuitry, and a plurality of output circuits. Each of the plurality of photodiode circuits is coupled to receive a different one of the plurality of transfer control signals as a proximate photodiode circuit, proximate in a first direction. The binning circuitry is coupled to electrically connect the plurality of photodiode circuits into groups of photodiode circuit sense nodes in response to a binning control signal. Each of the plurality of output circuits is coupled to one of the groups of photodiode circuit sense nodes. Each of the plurality of output circuits are coupled to receive the output charge from the photodiode circuits in the one of the groups of photodiode circuit sense nodes and output an output signal to a bitline in response to the output charge and an row select signal.
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公开(公告)号：US20200260031A1
公开(公告)日：2020-08-13
申请号：US16275092
申请日：2019-02-13
Applicant: OmniVision Technologies, Inc.
Inventor： Hiroaki Ebihara , Zheng Yang , Rui Wang , Teijun Dai
IPC: H04N5/378 , H04N5/3745
Abstract: An image sensor includes a pixel array including a plurality of pixels. Each pixel is coupled to generate image data in response to incident light. A bit line is coupled to a column of pixels of the pixel array and is separated into first and second portions. Each portion is coupled to a corresponding portion of rows of pixels of the pixel array. A readout circuit coupled to the bit line to read out the image data from the pixel array. The readout circuit includes a cascode device coupled between the first and second portions of the bit line. The cascode device is coupled to be biased to electrically separate the first and second portions of the bit line from one another such that a capacitance of each portion of the bit line does not affect a settling time of an other portion of the bit line.
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公开(公告)号：US10659055B1
公开(公告)日：2020-05-19
申请号：US16190862
申请日：2018-11-14
Applicant: OmniVision Technologies, Inc.
Inventor： Satoshi Sakurai , Hiroaki Ebihara
Abstract: An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M-L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.
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公开(公告)号：US20200153440A1
公开(公告)日：2020-05-14
申请号：US16190862
申请日：2018-11-14
Applicant: OmniVision Technologies, Inc.
Inventor： Satoshi Sakurai , Hiroaki Ebihara
Abstract: An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M−L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.
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Patent Agency Ranking
公开(公告)号：US10510796B1
公开(公告)日：2019-12-17
申请号：US16008434
申请日：2018-06-14
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Zheng Yang , Hiroaki Ebihara , Tiejun Dai
IPC: H01L27/146 , H04N5/355
Abstract: A group of shared pixels comprises: a first shared pixel comprising a first photodiode and a first transfer gate; a second shared pixel comprising a second photodiode and a second transfer gate; a third shared pixel comprising a third photodiode and a third transfer gate; a fourth shared pixel comprising a fourth photodiode and a first transfer gate; a first floating diffusion shared by the first shared pixel and the second shared pixel; a second floating diffusion shared by the third shared pixel and the fourth shared pixel; a capacitor coupled to the first floating diffusion through a first dual conversion gain transistor, and the second floating diffusion through a second dual conversion gain transistor; wherein the capacitor is formed in an area covering most of the first shared pixel, the second shared pixel, the third shared pixel, and the fourth shared pixel.
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公开(公告)号：US20190268556A1
公开(公告)日：2019-08-29
申请号：US16222832
申请日：2018-12-17
Applicant: OmniVision Technologies, Inc.
Inventor： Hiroaki Ebihara , Rui Wang , Zheng Yang , Eiichi Funatsu
IPC: H04N5/378 , H01L27/146
Abstract: An image sensor includes a pixel array including a plurality of pixels. A bit line coupled to a column of pixels is separated in to a plurality of electrically portions that are coupled to corresponding portions of rows of the pixel array. A first switching circuit of a readout circuit is coupled to the bit line. A first switching circuit is configured to couple a bit line current source to the bit line to provide a DC current coupled to flow through the bit line and through the first switching circuit during a readout operation of a pixel coupled to the bit line. A second switching circuit is configured to couple and ADC to the bit line during the readout operation of the pixel. Substantially none of the DC current provided by the bit line current source flows through the second switching circuit during the readout operation of the pixel.
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公开(公告)号：US20180324378A1
公开(公告)日：2018-11-08
申请号：US16035363
申请日：2018-07-13
Applicant: OmniVision Technologies, Inc.
Inventor： Hiroaki Ebihara , Zheng Yang
CPC classification number: H04N5/378 , H03K5/2481
Abstract: Apparatuses and method for an image sensor with increased analog to digital conversion range and reduced noise are described herein. An example method may include disabling a first auto-zero switch of a comparator, the first auto-zero switch coupled to auto-zero a reference voltage input of the comparator, adjusting an auto-zero offset voltage of a ramp voltage provided to the reference voltage input of the comparator, and disabling a second auto-zero switch of the comparator, the second auto-zero switch coupled to auto-zero a bitline input of the comparator.
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公开(公告)号：US10116892B1
公开(公告)日：2018-10-30
申请号：US15853487
申请日：2017-12-22
Applicant: OmniVision Technologies, Inc.
Inventor： Rui Wang , Hiroaki Ebihara
IPC: H04N5/235 , H04N5/374 , H01L27/146 , H04N5/378
Abstract: A photodiode is adapted to accumulate image charges in response to incident light. The accumulate image charges are transferred to a floating diffusion, amplified, row selected and the amplified row selected signal is output to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. A current source is coupled to connect between the bitline source node and a ground. The current source generator sinks adjustable current from the bitline source node to the ground through a cascode transistor and a bias transistor. A cascode hold capacitor is coupled between the cascode control voltage and the ground. A bias hold capacitor is coupled between the bias control voltage and the ground. A bias boost driver is coupled to control the cascode control voltage and the bias control voltage.
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79.发明申请公开(公告)号：US20180302578A1
公开(公告)日：2018-10-18
申请号：US15486896
申请日：2017-04-13
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Hiroaki Ebihara
IPC: H04N5/355 , H04N5/3745 , H04N5/378 , H04N5/243 , H01L27/12
CPC classification number: H01L27/1255 , H04N5/37452 , H04N5/378
Abstract: Example comparators as discussed herein may include a second stage coupled to provide an output in response to an intermediate voltage, a first stage coupled to provide the intermediate voltage in response to an input. The first stage including a pair of cascode devices coupled to a current mirror, a low gain input coupled to inputs of the first stage via first switches, and further selectively coupled to the pair of cascode devices via second switches, and a high gain input coupled to the first and second inputs of the first stage via the first switches, and further selectively coupled to the pair of cascode devices via fourth switches. Based on a low conversion gain mode, the low gain input may be coupled to the inputs by the first switches, and further coupled to the pair of cascode devices by the second switches in response to a control signal being in a first state, and based on a high conversion gain mode, the high gain input may be coupled to the first and second inputs by the first switches, and further coupled to the pair of cascode device by the fourth switch in response to the control signal being in a second state.
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