-
公开(公告)号：US08742838B2
公开(公告)日：2014-06-03
申请号：US13123811
申请日：2009-04-17
Applicant: Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
Inventor： Ken Takeuchi , Tadashi Yasufuku , Koichi Ishida , Makoto Takamiya , Takayasu Sakurai
CPC classification number: G11C5/04 , G11C5/02 , G11C5/145 , G11C11/005 , G11C16/12 , G11C16/30 , H01L25/0657 , H01L25/16 , H01L25/18 , H01L2225/06513 , H01L2225/06517 , H01L2924/0002 , H01L2924/19106 , H01L2924/00
Abstract: The interposer 30 is disposed on an upper surface of the stacked structure 24 formed by stacking a plurality of a DRAM chip 20 and a plurality of a flash memory chip 22. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit 40. Thus down-size of the entire device is accomplished.
Abstract translation: 插入器30设置在通过堆叠多个DRAM芯片20和多个闪存芯片22而形成的堆叠结构24的上表面上。因此，可以实现整个装置的尺寸缩小。 具有电感器的升压转换器被用作升压电路40.因此，可以实现整个装置的小型化。
-
公开(公告)号：US08223558B2
公开(公告)日：2012-07-17
申请号：US13179714
申请日：2011-07-11
Applicant: Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
Inventor： Tomoharu Tanaka , Hiroshi Nakamura , Ken Takeuchi , Riichiro Shirota , Fumitaka Arai , Susumu Fujimura
CPC classification number: G11C16/0483 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345 , G11C16/3454 , G11C16/3459 , G11C16/3463 , G11C2211/5621
Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.
Abstract translation: NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。
-
公开(公告)号：US20120075903A1
公开(公告)日：2012-03-29
申请号：US13310148
申请日：2011-12-02
Applicant: Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
Inventor： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC: G11C5/06
CPC classification number: G11C16/0483 , G11C16/10
Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.
Abstract translation: 选择栅极晶体管具有由第一级导电层和第二级导电层构成的选择栅电极。 第一级导电层具有接触区域。 第二级导电层的部分被去除，位于接触区域上方。 在列方向上彼此相邻的两个相邻的选择栅电极被布置成使得一个选择栅电极的接触区域不与另一个选择栅电极的接触区域相对。 一个选择栅电极在其与另一个选择栅电极的接触区域相对的部分中移除其第一和第二级导电层。
-
公开(公告)号：US08144513B2
公开(公告)日：2012-03-27
申请号：US12960882
申请日：2010-12-06
Applicant: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
Inventor： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
CPC classification number: G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。
-
公开(公告)号：US08139388B2
公开(公告)日：2012-03-20
申请号：US12565477
申请日：2009-09-23
Applicant: Mitsue Takahashi , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
Inventor： Mitsue Takahashi , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
IPC: G11C11/22
CPC classification number: G11C11/22 , G11C11/223 , G11C11/5657
Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources.The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
Abstract translation: 本发明的目的是提供一种能够在不需要准备多个电压源的情况下在FeFET单元中进入多值存储的非易失性半导体存储装置。 非易失性半导体存储装置设置有多值铁电存储单元，其通过施加具有一个相同的高度和变化的宽度的脉冲电压而向铁电体材料施加不同数量的极化，并因此根据偏振极化量产生不同的存储状态 。
-
公开(公告)号：US20110075488A1
公开(公告)日：2011-03-31
申请号：US12960882
申请日：2010-12-06
Applicant: Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
Inventor： Koji Hosono , Hiroshi Nakamura , Ken Takeuchi , Kenichi Imamiya
IPC: G11C16/04
CPC classification number: G11C16/0483 , G11C5/145 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.
Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。
-
公开(公告)号：US07864592B2
公开(公告)日：2011-01-04
申请号：US12551936
申请日：2009-09-01
Applicant: Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
Inventor： Ken Takeuchi , Tomoharu Tanaka , Noboru Shibata
IPC: G11C16/06
CPC classification number: G11C16/3418 , G11C7/1051 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5643 , G11C2211/5649 , G11C2211/565 , G11C2216/14
Abstract: Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.
-
78.发明申请SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD 有权具有高操作可靠性和高效率的芯片实现的半导体存储器件
公开(公告)号：US20100309722A1
公开(公告)日：2010-12-09
申请号：US12855481
申请日：2010-08-12
Applicant: Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
Inventor： Hiroshi Nakamura , Ken Takeuchi , Hideko Oodaira , Kenichi Imamiya , Kazuhito Narita , Kazuhiro Shimizu , Seiichi Aritome
IPC: G11C16/02
CPC classification number: G11C5/063 , G11C16/0483 , G11C16/08 , G11C2029/0403 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524
Abstract: A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
Abstract translation: 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而引起的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。
-
公开(公告)号：US07729178B2
公开(公告)日：2010-06-01
申请号：US11849891
申请日：2007-09-04
Applicant: Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
Inventor： Yasushi Kameda , Ken Takeuchi , Hitoshi Shiga , Takuya Futatsuyama , Koichi Kawai
IPC: G11C7/10
CPC classification number: G11C16/102
Abstract: The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.
Abstract translation: 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。
-
公开(公告)号：US20100073988A1
公开(公告)日：2010-03-25
申请号：US12565477
申请日：2009-09-23
Applicant: Mitsue TAKAHASHI , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
Inventor： Mitsue TAKAHASHI , Shigeki Sakai , Shouyu Wang , Ken Takeuchi
CPC classification number: G11C11/22 , G11C11/223 , G11C11/5657
Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources.The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.
Abstract translation: 本发明的目的是提供一种能够在不需要准备多个电压源的情况下在FeFET单元中进入多值存储的非易失性半导体存储装置。 非易失性半导体存储装置设置有多值铁电存储单元，其通过施加具有一个相同的高度和变化的宽度的脉冲电压而向铁电体材料施加不同数量的极化，并因此根据偏振极化量产生不同的存储状态 。
