公开(公告)号：US09430105B2

公开(公告)日：2016-08-30

申请号：US14194363

申请日：2014-02-28

Applicant: Apple Inc.

Inventor： Weijun Yao ,  Taif A. Syed ,  Yingxuan Li ,  Ahmad Al-Dahle

IPC: G06F3/044 ,  G06F3/041 ,  G06F3/047

CPC classification number: G06F3/044 ,  G06F3/0418 ,  G06F3/047 ,  G06F2203/04101 ,  G06F2203/04112

Abstract: A self-capacitance touch sensor panel including a plurality of touch electrodes and one or more sense circuits coupled to the touch electrodes. The touch sensor panel also includes at least one offset cancellation circuit coupled to at least one of the touch electrodes and configured to generate an offset cancellation signal to cancel an offset signal at the at least one touch electrode. In some examples, the offset cancellation signal can be an offset cancellation current to cancel an offset current. In some examples, the offset cancellation circuit comprises a variable resistor, and a magnitude of the offset cancellation current is based on a resistance of the variable resistor. In some examples, each touch electrode is coupled to an offset cancellation circuit. In other examples, a single offset cancellation circuit is shared by a plurality of touch electrodes.

Abstract translation: 一种自电容式触摸传感器面板，包括多个触摸电极和耦合到触摸电极的一个或多个感测电路。 触摸传感器面板还包括耦合到至少一个触摸电极的至少一个偏移消除电路，并被配置为产生偏移消除信号以抵消在至少一个触摸电极处的偏移信号。 在一些示例中，偏移消除信号可以是消除偏移电流的偏移消除电流。 在一些示例中，偏移消除电路包括可变电阻器，并且偏移消除电流的大小基于可变电阻器的电阻。 在一些示例中，每个触摸电极耦合到偏移消除电路。 在其他示例中，单个偏移消除电路由多个触摸电极共享。

公开(公告)号：US09417749B2

公开(公告)日：2016-08-16

申请号：US14929120

申请日：2015-10-30

Applicant: Apple Inc.

Inventor： Shih Chang Chang ,  Hopil Bae ,  Cheng-ho Yu ,  Ahmad Al-Dahle ,  Abbas Jamshidi-Roudbari

IPC: G06F3/044 ,  G06F3/041 ,  G06F3/045

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/045

Abstract: Setting a slew rate, e.g., a rising time or a falling time, of a scanning signal can be performed with a first operation, and a shunting resistance of the scanning line can be set with a second operation. A scanning system that scans a display screen, a touch screen, etc., can set a desired slew rate during a first period of time and can set a desired shunting resistance during a second period of time. A gate line system can sequentially scan gate lines to display an image during a display phase of a touch screen. The gate line system can, for example, increase the falling times of gate line signals. After the falling gate line signal has stabilized, for example, the gate line system can decrease the shunting resistance of the gate line.

Abstract translation: 可以通过第一操作来执行扫描信号的转换速率，例如上升时间或下降时间，并且可以通过第二操作来设置扫描线的分流电阻。 扫描显示屏，触摸屏等的扫描系统可以在第一时间段期间设置期望的转换速率，并且可以在第二时间段期间设置期望的分流电阻。 栅极线系统可以在触摸屏的显示阶段中顺序地扫描栅极线以显示图像。 栅极线系统可以例如增加栅极线信号的下降时间。 在下降的栅极线信号稳定之后，例如，栅极线系统可以降低栅极线的分流电阻。

公开(公告)号：US08803593B2

公开(公告)日：2014-08-12

申请号：US13632078

申请日：2012-09-30

Applicant: Apple Inc.

Inventor： Ahmad Al-Dahle ,  Yafei Bi ,  Mir B. Ghaderi ,  Wei H. Yao

IPC: G05F1/10

CPC classification number: G05F1/613

Abstract: One embodiment of an apparatus to control and sense a voltage through a single node can include a comparator to monitor single node voltage, a transistor to discharge voltage through the single node and control logic. The control logic can have at least two operational phases when actively controlling the voltage through the single node. In a first phase, the control logic can configure the comparator to determine if the single node voltage is greater than a reference voltage. In a second phase, the control logic can configure the transistor to discharge voltage through the single node when the comparator has previously indicated that the single node voltage is greater than a reference voltage. The control logic can alternatively execute first and second phases to discharge the voltage to a predetermined level.

Abstract translation: 用于控制和感测通过单个节点的电压的装置的一个实施例可包括监视单节点电压的比较器，通过单个节点放电电压的晶体管和控制逻辑。 当通过单个节点主动控制电压时，控制逻辑可以具有至少两个操作阶段。 在第一阶段中，控制逻辑可以配置比较器以确定单个节点电压是否大于参考电压。 在第二阶段中，当比较器先前已经指示单个节点电压大于参考电压时，控制逻辑可以配置晶体管以通过单个节点放电电压。 控制逻辑可替代地执行第一和第二阶段以将电压放电至预定水平。

公开(公告)号：US20140062940A1

公开(公告)日：2014-03-06

申请号：US13679793

申请日：2012-11-16

Applicant: APPLE INC.

Inventor： Ahmad Al-Dahle ,  Yafei Bi ,  Mir B. Ghaderi

IPC: G06F3/044 ,  G09G3/36

CPC classification number: G06F3/044 ,  G06F3/0412 ,  G06F3/0416 ,  G09G3/36

Abstract: Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Abstract translation: 用于监视显示器的内部电阻的系统和方法可以包括经由电容器向显示器提供第一电压和第二电压，第二电压被配置为使得显示器能够分别接收触摸输入和显示图像数据。 该方法可以经由第一电阻器，第二电阻器以及彼此并联耦合的第一电阻器和第二电阻器至少三次放电电容器。 该方法可以监视对应于电容器通过第一电阻器，第二电阻器以及第一电阻器和第二电阻器彼此并联耦合而从第一电压放电到第二电压的三个放电波形。 至少部分地基于放电波形，该方法可以确定对应于显示器的内部电阻的玻璃电阻值的芯片和玻璃电阻值的弯曲。

公开(公告)号：US20130342431A1

公开(公告)日：2013-12-26

申请号：US13715702

申请日：2012-12-14

Applicant: APPLE INC.

Inventor： Saman Saeedi ,  Shafiq M. Jamal ,  Ahmad Al-Dahle

IPC: G09G3/36 ,  G09G3/00

CPC classification number: G09G3/3607 ,  G09G3/006 ,  G09G3/3655 ,  G09G2320/0204 ,  G09G2320/0219 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2320/029 ,  G09G2320/0295 ,  G09G2320/041 ,  G09G2320/0626 ,  G09G2320/0693 ,  G09G2330/12

Abstract: Systems, methods, and devices are provided to reduce or eliminate mura artifacts on electronic displays. For example, pixels may be programmed to a uniform gray level before all or a substantial number of gates of the pixels are activated. The voltages on some or all source lines that supply the pixels may be measured. A mura artifact may be seen when voltage differences on the source lines are present. As such, operational parameters of the electronic display may be adjusted to reduce or eliminate the mura artifact by reducing the voltage differences.

Abstract translation: 提供系统，方法和设备以减少或消除电子显示器上的mura伪影。 例如，像素可以在所有或相当数量的像素的栅极被激活之前被编程为均匀的灰度级。 可以测量供应像素的一些或所有源极线上的电压。 当存在源极线上的电压差时，可能会看到一个阴影伪像。 因此，可以调整电子显示器的操作参数，以通过减小电压差来减少或消除凹陷伪影。

公开(公告)号：US20130328847A1

公开(公告)日：2013-12-12

申请号：US13654242

申请日：2012-10-17

Applicant: APPLE INC.

Inventor： Ahmad Al-Dahle ,  Hopil Bae ,  Sang Y. Youn ,  Yafei Bi ,  Wei H. Yao ,  David A. Stronks

IPC: G09G5/00

CPC classification number: G09G5/003 ,  G09G3/2092 ,  G09G2330/027 ,  G09G2330/06

Abstract: Methods and devices employing mura prevention circuitry, are provided. In one example, a method may include supplying a first voltage pathway between a common electrode driver and a common electrode of an electronic display device and supplying a second voltage pathway between the common electrode driver and ground. Mura prevention circuitry may be supplied that activates the first voltage pathway when the electronic display device is turned on and an activation gate signal is provided from a gate corresponding to the common electrode driver. Further, the mura prevention circuitry may activate the second voltage pathway when the electronic display device is turned off or no activation gate signal is provided from the gate corresponding to the common electrode driver.

Abstract translation: 提供了采用mura预防电路的方法和装置。 在一个示例中，方法可以包括在公共电极驱动器和电子显示装置的公共电极之间提供第一电压路径，并且在公共电极驱动器和地之间提供第二电压路径。 可以提供Mura防止电路，其在电子显示装置接通时激活第一电压通路，并且从对应于公共电极驱动器的门提供激活门信号。 此外，当电子显示装置关闭或从对应于公共电极驱动器的门提供激活栅极信号时，防护电路可以激活第二电压路径。