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    Write driver circuits for resistive random access memory (RAM) arrays
    61.
    发明授权
    Write driver circuits for resistive random access memory (RAM) arrays 有权
    为电阻随机存取存储器（RAM）阵列写入驱动电路

    公开(公告)号：US09583171B2

    公开(公告)日：2017-02-28

    申请号：US14644631

    申请日：2015-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Jung Pill Kim ,  Sungryul Kim ,  Taehyun Kim

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/79 ,  G11C2213/82

    Abstract: Aspects disclosed in the detailed description include write driver circuits for resistive random access memory (RAM) arrays. In one aspect, a write driver circuit is provided to facilitate writing data into a resistive RAM array in a memory system. The write driver circuit is coupled to a selector circuit configured to select a memory bitcell(s) in the resistive RAM array for a write operation. An isolation circuit is provided in the write driver circuit to couple a current source to the selector circuit to provide a write voltage during the write operation and to isolate the current source from the selector circuit when the selector circuit is not engaged in the write operation. By isolating the selector circuit from the current source when the selector circuit is on standby, it is possible to reduce leakage current in the selector circuit, thus reducing standby power consumption in the memory system.

    Abstract translation: 在详细描述中公开的方面包括用于电阻随机存取存储器（RAM）阵列的写入驱动器电路。 在一个方面，提供写入驱动器电路以便于将数据写入存储器系统中的电阻式RAM阵列。 写驱动器电路耦合到选择器电路，其被配置为选择用于写入操作的电阻RAM阵列中的存储器位单元。 在写入驱动器电路中提供隔离电路，以将电流源耦合到选择器电路以在写入操作期间提供写入电压，并且当选择器电路未被接合在写入操作中时将电流源与选择器电路隔离。 当选择器电路处于待机状态时，通过将选择器电路与电流源隔离，可以减少选择器电路中的漏电流，从而降低存储系统的待机功耗。

    Non-volatile memory with overwrite capability and low write amplification
    62.
    发明授权
    Non-volatile memory with overwrite capability and low write amplification 有权
    具有覆盖能力和低写入放大率的非易失性存储器

    公开(公告)号：US09576616B2

    公开(公告)日：2017-02-21

    申请号：US13952467

    申请日：2013-07-26

    Applicant: Crossbar, Inc.

    Inventor： Hagop Nazarian ,  Sang Nguyen

    IPC: G11C7/00 ,  G11C13/00

    CPC classification number: G11C7/00 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/78 ,  Y10T29/49002

    Abstract: Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations.

    Abstract translation: 本文描述了具有向存储系统提供低写入放大的写入和覆盖能力的非易失性存储器架构。 作为示例，公开了包括两端存储器单元的块和子块的存储器阵列。 在一些实施例中，可以直接覆盖两端存储单元，从而有助于低至一的写入放大值。 此外，存储器阵列可以具有输入输出多路复用器配置，从而在存储器操作期间减少存储器架构的潜行路径电流。

    Memory system
    64.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US09570181B2

    公开(公告)日：2017-02-14

    申请号：US15058828

    申请日：2016-03-02

    Applicant: KABUSHIKI KAISHA TOSHIBA

    Inventor： Takao Marukame ,  Kazuya Matsuzawa ,  Yoshifumi Nishi ,  Jiezhi Chen ,  Yusuke Higashi ,  Yuuichiro Mitani

    IPC: G11C16/14 ,  G11C16/10 ,  G11C16/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C13/00

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C13/0002 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C2213/72 ,  G11C2213/77

    Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.

    Abstract translation: 根据实施例，存储器系统包括第一布线; 第二布线; 第三条布线; 第四条接线; 第一和第二存储。 第一存储器包括布置在第一布线和第二布线的交点处的第一存储单元。 每个第三布线连接到第一布线中的任一个。 第四布线中的每一条与由主机设备指定的逻辑地址预先关联。 第二存储器包括布置在第三布线和第四布线的交叉处的第二存储单元。 根据逻辑地址和第一布线之间的对应关系，将第二存储单元中的每一个的电阻状态设置为第一电阻状态或电阻值低于第一电阻状态的第二电阻状态 。

    HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY
    65.
    发明申请
    HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY 有权
    用于跨点阵列的高电压开关电路

    公开(公告)号：US20170025173A1

    公开(公告)日：2017-01-26

    申请号：US15090216

    申请日：2016-04-04

    Applicant: Unity Semiconductor Corporation

    Inventor： Christophe Chevallier ,  Chang Hua Siau

    IPC: G11C13/00 ,  G11C8/10 ,  H03K19/0185 ,  H03K3/356

    CPC classification number: G11C13/0023 ,  G11C8/08 ,  G11C8/10 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77 ,  H03K3/356104 ,  H03K19/018521

    Abstract: A system includes a cross-point memory array and a decoder circuit coupled to the cross-point memory array. The decoder circuit includes a predecoder having predecode logic to generate a control signal and a level shifter circuit to generate a voltage signal. The decoder circuit further includes a post-decoder coupled to the predecoder, the post-decoder including a first stage and a second stage coupled to the first stage, the control signal to control the first stage and the second stage to route the voltage signal through the first stage and the second stage to a selected conductive array line of a plurality of conductive array lines coupled to a memory array.

    Abstract translation: 系统包括交叉点存储器阵列和耦合到交叉点存储器阵列的解码器电路。 解码器电路包括具有用于产生控制信号的预解码逻辑的预解码器和产生电压信号的电平移位器电路。 解码器电路还包括耦合到预解码器的后解码器，后解码器包括耦合到第一级的第一级和第二级，控制信号以控制第一级和第二级以将电压信号通过 第一级和第二级连接到耦合到存储器阵列的多个导电阵列线的选定导电阵列线。

    NON-VOLATILE MEMORY WITH ADJUSTABLE CELL BIT SHAPE
    66.
    发明申请
    NON-VOLATILE MEMORY WITH ADJUSTABLE CELL BIT SHAPE 审中-公开
    具有可调节单元形状的非易失性存储器

    公开(公告)号：US20170018307A1

    公开(公告)日：2017-01-19

    申请号：US15280110

    申请日：2016-09-29

    Applicant: HGST Netherlands B.V.

    Inventor： Luiz M. FRANCA-NETO ,  Kurt Allan RUBIN

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0023 ,  G11C2013/0092 ,  G11C2213/53

    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

    Abstract translation: 本公开的实施例一般涉及非易失性存储器，特别是涉及可调节单元位形状的非易失性存储器。 在一个实施例中，提供了可调整的存储单元。 存储单元通常包括栅电极，至少一个记录层和沟道层。 沟道层通常能够支撑耗尽区并且设置在栅电极和至少一个记录层之间。 在该实施例中，在激活栅极时，沟道层可能被耗尽，并且最初流过沟道的电流可以被引导通过至少一个记录层。

    ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS
    67.
    发明申请
    ARRAY VOLTAGE REGULATING TECHNIQUE TO ENABLE DATA OPERATIONS ON LARGE MEMORY ARRAYS WITH RESISTIVE MEMORY ELEMENTS 有权
    使用电阻式电压调节技术实现数据操作，具有电阻记忆元件的大容量存储器阵列

    公开(公告)号：US20170010831A1

    公开(公告)日：2017-01-12

    申请号：US15213756

    申请日：2016-07-19

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Chang Hua Siau

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/06 ,  G11C8/08 ,  G11C11/419 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/72

    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to preserve states of memory elements in association with data operations using variable access signal magnitudes for other memory elements, such as implemented in third dimensional memory technology. In some embodiments, a memory device can include a cross-point array with resistive memory elements. An access signal generator can modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. A tracking signal generator is configured to track the modified magnitude of the signal and to apply a tracking signal to other resistive memory elements associated with other subsets of bit lines, the tracking signal having a magnitude at a differential amount from the modified magnitude of the signal.

    Abstract translation: 本发明的实施例大体上涉及半导体和存储器技术，更具体地涉及系统，集成电路和保持存储器元件的状态的方法，该数据与使用其他存储器元件的可变访问信号幅度的数据操作相关联，例如在第三 三维存储技术。 在一些实施例中，存储器件可以包括具有电阻存储元件的交叉点阵列。 访问信号发生器可以修改信号的幅度以产生用于信号访问与字线和位线的子集相关联的电阻性存储器元件的修改幅度。 跟踪信号发生器被配置为跟踪信号的经修改的幅度，并将跟踪信号施加到与其他子位位线相关联的其他电阻性存储元件，跟踪信号具有与信号的修改幅度不同的量级 。

    Enhanced temperature compensation for resistive memory cell circuits
    70.
    发明授权
    Enhanced temperature compensation for resistive memory cell circuits 有权
    增强电阻式存储单元电路的温度补偿

    公开(公告)号：US09520189B1

    公开(公告)日：2016-12-13

    申请号：US14926569

    申请日：2015-10-29

    Applicant: International Business Machines Corporation

    Inventor： Nikolaos Papandreou ,  Charalampos Pozidis ,  Milos Stanisavljevic

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

    CPC classification number: G11C13/0033 ,  G11C7/04 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0021 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069

    Abstract: In some aspects, a computer-implemented method for performing a voltage-based measurement of a resistive memory cell includes a plurality m of programmable cell states. The method may include providing, via a processor, a prebiased voltage at a connecting node coupled to the resistive memory cell, coupling, via the processor, a resistor circuit in parallel to the resistive memory cell such that the resistor is configured to reduce an effective resistance at the connecting node of the prebiasing circuit, prebiasing a bitline capacitance of the resistive memory cell by the prebiasing circuit, settling, via the processor, a sensing circuit to a target voltage by connecting the sensing circuit to one of a plurality of settling circuits, wherein the one of the plurality of settling circuits is selected based on a temperature reading of the resistive memory cell, sensing a voltage of the resistive memory cell, and outputting a resultant value based on the sensed voltage.

    Abstract translation: 在一些方面，用于执行电阻式存储器单元的基于电压的测量的计算机实现的方法包括多个可编程单元状态。 该方法可以包括经由处理器在耦合到电阻存储器单元的连接节点处提供预偏置电压，经由处理器与电阻存储器单元并联地耦合电阻器电路，使得电阻器被配置为减少有效 在偏置电路的连接节点处的电阻，通过预偏置电路预先偏置电阻存储器单元的位线电容，通过将感测电路连接到多个稳定电路之一，经由处理器将感测电路稳定到目标电压 其中，基于所述电阻性存储单元的温度读数来选择所述多个稳定电路中的一个，感测所述电阻存储单元的电压，并基于所感测的电压输出所得到的值。

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