公开(公告)号：US20050010888A1

公开(公告)日：2005-01-13

申请号：US10604279

申请日：2003-07-08

申请人： Jack Smith ,  Sebastian Ventrone

发明人： Jack Smith ,  Sebastian Ventrone

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5045

摘要： The disclosure presents a method of designing an integrated circuit having latches. The invention first prepares a logical design of logic devices and latches and then creates a physical design by positioning the logic devices and the latches within the integrated circuit based on the logical design. During the process of creating the physical design the invention eliminates redundant latches by combining latches which do not transition during the same clock cycle, latches which do not relate to the same logical function, latches which are in the same clock domain, and latches that are within a given physical proximity of each other. The invention determines whether latches transition during the same clock cycle by running a simulation of an initial physical design and recording the latches that transition during each clock cycle. The invention also determines whether an adequate timing slack exists between transitions of latches that do not transition during the same clock cycle. The foregoing process of eliminating redundant latches comprises replacing at least two latches with a single latch. The process of eliminating redundant latches produces a revised physical design, and the invention tests the revised physical design to determine whether the revised physical design performs as expected.

摘要翻译： 本公开提供了一种设计具有锁存器的集成电路的方法。 本发明首先准备逻辑设备和锁存器的逻辑设计，然后基于逻辑设计将逻辑器件和锁存器定位在集成电路内，从而创建物理设计。 在创建物理设计的过程中，本发明通过组合在同一时钟周期内不转换的锁存器来消除冗余锁存器，与相同逻辑功能不相关的锁存器，处于相同时钟域的锁存器和锁存器 在彼此的给定物理接近度内。 本发明通过运行初始物理设计的模拟并且记录在每个时钟周期期间转换的锁存器来确定锁存器是否在同一时钟周期内转变。 本发明还确定在相同时钟周期期间不转换的锁存器的转换之间是否存在适当的定时松弛。 消除冗余锁存器的上述过程包括用单个锁存器替换至少两个锁存器。 消除冗余锁存器的过程产生修改的物理设计，并且本发明测试修改的物理设计以确定修改后的物理设计是否按预期执行。