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    Power semiconductor device
    51.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号：US08723228B1

    公开(公告)日：2014-05-13

    申请号：US13796688

    申请日：2013-03-12

    Applicant: LG Innotek Co., Ltd.

    Inventor： Jung Hun Oh

    IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC classification number: H01L29/0646 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/34 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A power semiconductor device is disclosed. The power semiconductor device includes a substrate, a first semiconductor layer disposed on the substrate, a second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer disposed on the second semiconductor layer and exposing a portion of the second semiconductor layer, a gate electrode disposed on the portion of the second semiconductor layer exposed via the third semiconductor layer, and a source electrode and a drain electrode disposed on the third semiconductor layer at both sides of the gate electrode to be spaced apart from each other. An electrical segregation region is formed in the third semiconductor layer between the gate electrode and the drain electrode.

    Abstract translation: 公开了功率半导体器件。 功率半导体器件包括衬底，设置在衬底上的第一半导体层，设置在第一半导体层上的第二半导体层，设置在第二半导体层上并暴露第二半导体层的一部分的第三半导体层，栅极 设置在经由第三半导体层露出的第二半导体层的部分上的电极以及设置在栅电极两侧彼此间隔开的第三半导体层上的源电极和漏电极。 在栅电极和漏电极之间的第三半导体层中形成电偏析区域。

    Semiconductor device
    52.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08723224B2

    公开(公告)日：2014-05-13

    申请号：US13620088

    申请日：2012-09-14

    Applicant: Nobuyuki Ito ,  John Kevin Twynam

    Inventor： Nobuyuki Ito ,  John Kevin Twynam

    IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC classification number: H01L29/7783 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7787

    Abstract: One embodiment of a semiconductor device according to the present invention includes a substrate, a base compound semiconductor layer layered on the substrate to form a base, a channel defining compound semiconductor layer layered on the base compound semiconductor layer to define a channel, and an impact ionization control layer that is layered within a layering range of the base compound semiconductor layer and controls the location of impact ionization, wherein the base compound semiconductor layer is formed of a first compound semiconductor, the channel defining compound semiconductor layer is formed of a second compound semiconductor, and the impact ionization control layer is formed of a third compound semiconductor that has a smaller band gap than the first compound semiconductor.

    Abstract translation: 根据本发明的半导体器件的一个实施例包括衬底，在衬底上层叠以形成基底的基底化合物半导体层，在基底化合物半导体层上层叠以限定沟道的限定化合物半导体层的沟道和冲击 电离控制层，其层叠在所述基底化合物半导体层的层叠范围内，并控制所述冲击电离的位置，其中所述基底化合物半导体层由第一化合物半导体形成，所述沟道限定化合物半导体层由第二化合物 并且所述碰撞电离控制层由具有比所述第一化合物半导体更小的带隙的第三化合物半导体形成。

    SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
    54.
    发明申请
    SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS 审中-公开
    固态成像装置和电子装置

    公开(公告)号：US20140008745A1

    公开(公告)日：2014-01-09

    申请号：US13926355

    申请日：2013-06-25

    Applicant: Sony Corporation

    Inventor： Shunsuke Maruyama

    IPC: H01L31/0328

    CPC classification number: H01L31/0328 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1469 ,  H01L31/0322 ,  H01L31/105 ,  Y02E10/541 ,  Y02P70/521

    Abstract: There is provided a solid-state imaging device including a pixel substrate in which a wire layer and a semiconductor element are formed using a wire material which can endure temperature at a time of forming a photoelectric conversion layer, and a logic substrate in which a semiconductor element is formed. The wire layer side of the pixel substrate is joined to a rear side of the logic substrate, and, after the photoelectric conversion layer is formed on a rear side of the pixel substrate, a wire layer is formed in the logic substrate such that the wire layers are disposed on a front side of the pixel substrate and the photoelectric conversion layer is disposed on the rear side of the pixel substrate.

    Abstract translation: 提供了一种固态成像装置，其包括像素基板，其中使用能够在形成光电转换层时承受温度的线材形成线层和半导体元件;以及逻辑基板，其中半导体 元件形成。 像素基板的导线层侧与逻辑基板的背面接合，在像素基板的背面形成光电转换层之后，在逻辑基板上形成导线层， 层设置在像素基板的前侧，光电转换层设置在像素基板的后侧。

    Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor
    55.
    发明授权
    Pseudo buried layer and manufacturing method of the same, deep hole contact and bipolar transistor 有权
    伪埋层及其制造方法相同，深孔接触和双极晶体管

    公开(公告)号：US08592870B2

    公开(公告)日：2013-11-26

    申请号：US13227387

    申请日：2011-09-07

    Applicant: Donghua Liu ,  Wensheng Qian

    Inventor： Donghua Liu ,  Wensheng Qian

    IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288

    CPC classification number: H01L29/0821 ,  H01L21/28525 ,  H01L21/7684 ,  H01L29/0657 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7378

    Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.

    Abstract translation: 本发明公开了一种伪埋层，深孔接触和双极晶体管，并且还公开了一种伪掩埋层的制造方法，包括：蚀刻硅衬底以形成有源区和浅沟; 顺序地将磷离子和砷离子注入浅沟槽的底部以形成磷杂质区和砷杂质区; 对磷杂质区域和砷杂质区域进行热退火。 采用具有快速热扩散的磷和具有缓慢热扩散的砷的伪掩埋层的注入可以改善伪埋层表面的杂质浓度，降低伪掩埋层的薄层电阻，形成良好的欧姆接触 在伪埋层和深孔之间，减小接触电阻，提高三极管器件的频率特性和电流输出。

    PHOTOELECTRIC CONVERSION DEVICE AND SOLAR CELL HAVING THE SAME
    56.
    发明申请
    PHOTOELECTRIC CONVERSION DEVICE AND SOLAR CELL HAVING THE SAME 审中-公开
    光电转换装置和具有该光电转换装置的太阳能电池

    公开(公告)号：US20130269779A1

    公开(公告)日：2013-10-17

    申请号：US13912075

    申请日：2013-06-06

    Applicant: FUJIFILM CORPORATION

    Inventor： Tetsuo KAWANO ,  Hiroshi KAGA

    IPC: H01L31/0328

    CPC classification number: H01L31/0328 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541

    Abstract: The photoelectric conversion device of the present invention is a photoelectric conversion device which includes a substrate on which the following are layered in the order listed below: a lower electrode layer; a photoelectric conversion semiconductor layer which includes, as a major component, at least one kind of compound semiconductor having a chalcopyrite structure formed of a group Ib element, a group IIIb element, and a group VIb element; a buffer layer; and a transparent conductive layer, in which a carbonyl ion is provided on a surface of the buffer layer on the side of the transparent conductive layer and the buffer layer is a thin film layer having an average film thickness of 10 nm to 70 nm and includes a ternary compound of a cadmium-free metal, oxygen, and sulfur.

    Abstract translation: 本发明的光电转换装置是一种光电转换装置，其包括以下列顺序层叠以下的基板：下电极层; 作为主要成分的至少一种具有由Ib族元素，IIIb族元素和VIb族元素形成的黄铜矿结构的化合物半导体的光电转换半导体层， 缓冲层; 以及透明导电层，其中在透明导电层一侧的缓冲层的表面上设置羰基离子，缓冲层是平均膜厚为10nm〜70nm的薄膜层，并且包括 无镉金属，氧和硫的三元化合物。

    Heterojunction bipolar transistors with reduced base resistance
    58.
    发明授权
    Heterojunction bipolar transistors with reduced base resistance 有权
    具有降低的基极电阻的异质结双极晶体管

    公开(公告)号：US08513706B2

    公开(公告)日：2013-08-20

    申请号：US13672040

    申请日：2012-11-08

    Applicant: International Business Machines Corporation

    Inventor： Erik M. Dahlstrom ,  Peter B. Gray ,  Qizhi Liu

    IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

    CPC classification number: H01L29/7378 ,  H01L29/66242

    Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.

    Abstract translation: 具有降低的基极电阻的异质结双极晶体管，以及用于BiCMOS集成电路的异质结双极晶体管和设计结构的制造方法。 异质结双极晶体管包括在本征基极和外部基极之间的导电层。 导电层由诸如硅化物的导电材料构成，其电阻率低于形成本征碱和非本征基的材料。

    Monolithic three terminal photodetector
    60.
    发明授权
    Monolithic three terminal photodetector 有权
    单片三端子光电探测器

    公开(公告)号：US08461624B2

    公开(公告)日：2013-06-11

    申请号：US12952023

    申请日：2010-11-22

    Applicant: Yun-chung N Na ,  Yimin Kang

    Inventor： Yun-chung N Na ,  Yimin Kang

    IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

    CPC classification number: H01L31/02005 ,  G02B6/4295 ,  G02B2006/12097 ,  H01L31/028 ,  H01L31/105 ,  H01L31/1075 ,  Y02E10/547

    Abstract: Photodetectors operable to achieve multiplication of photogenerated carriers at ultralow voltages. Embodiments include a first p-i-n semiconductor junction combined with a second p-i-n semiconductor junction to form a monolithic photodetector having at least three terminals. The two p-i-n structures may share either the p-type region or the n-type region as a first terminal. Regions of the two p-i-n structures doped complementary to that of the shared terminal form second and third terminals so that the first and second p-i-n structures are operable in parallel. A multiplication region of the first p-i-n structure is to multiply charge carriers photogenerated within an absorption region of the second p-i-n structure with voltage drops between the shared first terminal and each of the second and third terminals being noncumulative.

    Abstract translation: 光电检测器可操作以实现超低电压下的光生载流子的倍增。 实施例包括与第二p-i-n半导体结组合的第一p-i-n半导体结，以形成具有至少三个端子的单片光电检测器。 两个p-i-n结构可以共享p型区域或n型区域作为第一端子。 掺杂与共享终端的两个p-i-n结构的区域形成第二和第三端子，使得第一和第二p-i-n结构可并行操作。 第一p-i-n结构的乘法区域是在共享的第一端子和第二和第三端子的每一个之间的电压降是不累积的，以使在第二p-i-n结构的吸收区域内产生的电荷载流倍增。

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