-
公开(公告)号：US20240213169A1
公开(公告)日：2024-06-27
申请号：US18086265
申请日：2022-12-21
Applicant: Intel Corporation
Inventor： Bohan Shan , Haobo Chen , Yiqun Bai , Dingying Xu , Srinivas Venkata Ramanuja Pietambaram , Hongxia Feng , Gang Duan , Xiaoying Guo , Ziyin Lin , Bai Nie , Kyle Jordan Arrington , Jeremy D. Ecton , Brandon C. Marin
IPC: H01L23/538 , H01L21/48 , H01L21/56 , H01L23/15 , H01L23/31 , H01L23/498 , H01L23/64 , H10B80/00
CPC classification number: H01L23/5389 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/15 , H01L23/3128 , H01L23/49822 , H01L23/49838 , H01L23/5382 , H01L23/5386 , H01L23/645 , H10B80/00 , H01L24/32
Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer including a cavity formed through the glass core layer; a glass core layer active component die disposed in the cavity; a first buildup layer contacting a first surface of the glass core layer; a second buildup layer contacting a second surface of the glass core layer; and a mold layer contacting a surface of the first buildup layer. The mold layer includes a mold layer active component die disposed in the mold layer, and the first buildup layer includes electrically conductive interconnect providing electrical continuity between the glass core layer active component die and the mold layer active component die. The top surface active component die is attached to the top surface of the substrate and electrically connected to the mold layer active component die.
-
公开(公告)号：US20240205167A1
公开(公告)日：2024-06-20
申请号：US18587744
申请日：2024-02-26
Applicant: Intel Corporation
Inventor： Kevin Clark , Scott J. Weber , Ravi Prakash Gutala , Aravind Raghavendra Dasu
IPC: H04L49/109 , H01L23/538 , H01L25/065 , H04L49/15
CPC classification number: H04L49/109 , H01L25/0652 , H04L49/15 , H01L23/5386 , H01L2225/06513 , H01L2225/06517
Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
-
公开(公告)号：US12015019B2
公开(公告)日：2024-06-18
申请号：US17357459
申请日：2021-06-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jonathan Almeria Noquil , Makarand Ramkrishna Kulkarni
IPC: H01L25/00 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/16
CPC classification number: H01L25/16 , H01L23/3185 , H01L23/49822 , H01L23/49844 , H01L23/5383 , H01L23/5386 , H01L24/97
Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.
-
公开(公告)号：US12015004B2
公开(公告)日：2024-06-18
申请号：US18359425
申请日：2023-07-26
Applicant: NXP USA, Inc.
Inventor： Li Li , Lakshminarayan Viswanathan , Jeffrey Kevin Jones
IPC: H01L23/00 , H01L21/48 , H01L21/78 , H01L23/367 , H01L23/538
CPC classification number: H01L24/20 , H01L21/4853 , H01L21/4857 , H01L21/4871 , H01L21/78 , H01L23/367 , H01L23/5383 , H01L23/5386 , H01L24/02 , H01L24/19 , H01L2224/214 , H01L2924/10253 , H01L2924/10271 , H01L2924/1033 , H01L2924/13091 , H01L2924/19105
Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.
-
55.发明授权
公开(公告)号：US12014993B2
公开(公告)日：2024-06-18
申请号：US17341314
申请日：2021-06-07
Inventor： Chen-Hua Yu , Kuo-Chung Yee , Chun-Hui Yu
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/565 , H01L23/3107 , H01L23/5383 , H01L23/5386 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/214 , H01L2225/1035 , H01L2225/1058 , H01L2924/365
Abstract: Provided is a method of fabricating a package including: providing a die with a contact thereon; forming a redistribution layer (RDL) structure on the die, the forming the RDL structure on the die comprising: forming a first dielectric material on the die; forming a conductive feature in and partially on the first dielectric material; after the forming the conductive feature, forming a protective layer on the conductive feature, wherein the protective layer covers a top surface of the conductive feature and extends to cover a top surface of the first dielectric material; forming a second dielectric material on the protective layer; and performing a planarization process to expose the conductive feature; and forming a plurality of conductive connectors to electrically connect the die through the RDL structure.
-
公开(公告)号：US20240194671A1
公开(公告)日：2024-06-13
申请号：US18542240
申请日：2023-12-15
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege
IPC: H01L27/06 , G11C5/06 , H01L21/8238 , H01L23/538 , H01L25/065 , H01L27/092
CPC classification number: H01L27/0688 , G11C5/06 , H01L21/8238 , H01L23/5384 , H01L23/5386 , H01L25/0657 , H01L27/092
Abstract: Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.
-
57.发明公开
公开(公告)号：US20240194627A1
公开(公告)日：2024-06-13
申请号：US18584488
申请日：2024-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungmin Baek
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L23/13 , H01L23/31 , H01L23/498 , H01L23/538 , H01L25/00 , H01L25/10
CPC classification number: H01L24/20 , H01L21/4853 , H01L21/4857 , H01L21/568 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L25/105 , H01L25/50 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/16227 , H01L2224/2101 , H01L2224/2105 , H01L2224/211 , H01L2224/214 , H01L2224/215 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/0133 , H01L2924/04941 , H01L2924/04953 , H01L2924/15311 , H01L2924/1533 , H01L2924/19107
Abstract: A semiconductor device may include a seed structure on a complex structure. The seed structure may include a first barrier layer, a first seed layer on the first barrier layer, a second barrier layer on the first seed layer, and a second seed layer on the second barrier layer. The second barrier layer may contact a side surface of at least one of the first barrier layer and the first seed layer. An electrode layer may be disposed on the seed structure.
-
公开(公告)号：US12009354B2
公开(公告)日：2024-06-11
申请号：US17547455
申请日：2021-12-10
Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
Inventor： Ken Funaki
IPC: H01L25/18 , H01L23/00 , H01L23/538 , H01L25/00 , H01L25/065
CPC classification number: H01L25/18 , H01L23/5386 , H01L24/08 , H01L25/0655 , H01L25/50 , H01L24/06 , H01L24/94 , H01L2224/06152 , H01L2224/08145 , H01L2924/10156 , H01L2924/14511
Abstract: A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.
-
公开(公告)号：US12009351B2
公开(公告)日：2024-06-11
申请号：US17525833
申请日：2021-11-12
Applicant: Advanced Semiconductor Engineering, Inc.
Inventor： Wei-Hao Chang
IPC: H01L25/16 , H01L21/78 , H01L21/82 , H01L23/00 , H01L23/498 , H01L23/538 , H01L25/065 , H01L25/07 , H01L21/683
CPC classification number: H01L25/162 , H01L21/78 , H01L21/82 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/5386 , H01L24/12 , H01L24/15 , H01L24/97 , H01L25/0655 , H01L25/0657 , H01L25/072 , H01L25/074 , H01L25/165 , H01L21/6836 , H01L2225/1058 , H01L2924/181
Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a first substrate, a second substrate disposed over the first substrate and having a first surface facing away from the first substrate and a second surface facing the first substrate, a first component disposed on the first surface of the second substrate, a second component disposed on the second surface of the second substrate; and a support member covering the first component.
-
公开(公告)号：US20240186226A1
公开(公告)日：2024-06-06
申请号：US18439747
申请日：2024-02-12
Inventor： Soonheung BAE , Hyunjoung KIM
IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L23/13 , H01L23/31 , H01L23/538 , H01L25/065
CPC classification number: H01L23/49816 , H01L21/4853 , H01L21/565 , H01L23/13 , H01L23/3128 , H01L23/5386 , H01L23/5389 , H01L25/0652 , H01L25/0657 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586
Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.
