公开(公告)号：US11721624B2

公开(公告)日：2023-08-08

申请号：US16952345

申请日：2020-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Yuan Ting ,  Chung-Wen Wu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/7681 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure is directed to a semiconductor structure that includes a semiconductor substrate. A first interconnect layer is disposed over the semiconductor substrate. The first interconnect layer includes a first dielectric material having a conductive body embedded therein. The conductive body includes a first sidewall, a second sidewall, and a bottom surface. A spacer element has a sidewall which contacts the first sidewall of the conductive body and which contacts the bottom surface of the conductive body. A second interconnect layer overlies the first interconnect layer and includes a second dielectric material with at least one via therein. The at least one via is filled with a conductive material which is electrically coupled to the conductive body of the first interconnect layer.

公开(公告)号：US11710659B2

公开(公告)日：2023-07-25

申请号：US17646024

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Chieh Wu ,  Tang-Kuei Chang ,  Kuo-Hsiu Wei ,  Kei-Wei Chen ,  Ying-Lang Wang ,  Su-Hao Liu ,  Kuo-Ju Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Ting-Kui Chang ,  Chia Hsuan Lee

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/3115 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76825 ,  H01L23/5226 ,  H01L21/31155 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

公开(公告)号：US11705394B2

公开(公告)日：2023-07-18

申请号：US17751971

申请日：2022-05-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chin-Ling Huang

IPC: H01L23/525 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L23/5329 ,  H01L21/76807 ,  H01L21/76892 ,  H01L2924/0002 ,  H01L2924/09701

Abstract: The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

公开(公告)号：US20230207664A1

公开(公告)日：2023-06-29

申请号：US18116721

申请日：2023-03-02

Applicant: Intel Corporation

Inventor： Michael L. HATTENDORF ,  Curtis WARD ,  Heidi M. MEYER ,  Tahir GHANI ,  Christopher P. AUTH

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H10B10/00 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167

CPC classification number: H01L29/66545 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/7843 ,  H01L27/0886 ,  H01L21/76232 ,  H01L29/6656 ,  H01L29/0653 ,  H01L21/823431 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L21/76816 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785 ,  H01L29/165 ,  H01L21/76846 ,  H01L21/76849 ,  H01L29/7845 ,  H01L21/76834 ,  H01L29/41791 ,  H01L21/76801 ,  H10B10/12 ,  H01L29/0649 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5283 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7854 ,  H01L21/28518 ,  H01L23/5329 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/41783 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0922 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/76883 ,  H01L21/76885 ,  H01L29/665 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon, the fin having a lower fin portion and an upper fin portion. A first insulating layer is directly on sidewalls of the lower fin portion of the fin, wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen. A second insulating layer is directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin, the second insulating layer comprising silicon and nitrogen. A dielectric fill material is directly laterally adjacent to the second insulating layer directly on the first insulating layer directly on the sidewalls of the lower fin portion of the fin.

公开(公告)号：US20230207458A1

公开(公告)日：2023-06-29

申请号：US18046111

申请日：2022-10-12

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  David Ross Economy ,  Jay S. Brown ,  John D. Hopkins ,  Jordan D. Greenlee ,  Mithun Kumar Ramasahayam ,  Rita J. Klein

IPC: H01L23/528 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches. The method also includes recessing the first electrically conductive material and replacing removed portions of the first electrically conductive material with a second electrically conductive material.

公开(公告)号：US11688684B2

公开(公告)日：2023-06-27

申请号：US17576683

申请日：2022-01-14

Applicant: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.

Inventor： Hyunyoung Kim ,  Dowon Kwak ,  Kang-Won Seo

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5329 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53261 ,  H01L23/53266 ,  H01L21/28568

Abstract: A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor device includes a conductive structure that comprises: an upper conductive line arranged above and in electrical connection with a circuit component in a lower device layer through a via plug, wherein the upper conductive line extends laterally over the via plug; an interposing layer having a substantially uniform thickness arranged between the via plug and the upper conductive line, and extending laterally beyond a planar projection of the via plug, wherein the upper conductive line is in electrical connection with the via plug through the interposing layer; and an overlayer is disposed over the upper conductive line.

公开(公告)号：US20230197604A1

公开(公告)日：2023-06-22

申请号：US17845209

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： John Soo KIM ,  Min Wook CHUNG ,  Kyoung Suk KIM ,  Soo Kyung KIM ,  Won Suk LEE ,  Jong Jin LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76846 ,  H01L21/76877

Abstract: A semiconductor device is provided. The semiconductor device includes: a first interlayer insulating film defining a lower wiring trench; a lower wiring structure including a first lower barrier film which extends along sidewalls of the lower wiring trench, and a lower filling film which is on the first lower barrier film; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film defining an upper wiring trench which exposes at least part of the lower wiring structure; and an upper wiring structure provided in the upper wiring trench and connected to the lower wiring structure. An upper surface of the first lower barrier film is closer to a bottom surface of the lower wiring trench than each of an upper surface of the first interlayer insulating film and an upper surface the lower filling film. The upper surface of the first lower barrier film is concave.

公开(公告)号：US20230197603A1

公开(公告)日：2023-06-22

申请号：US17645402

申请日：2021-12-21

Applicant: International Business Machines Corporation

Inventor： Hsueh-Chung CHEN ,  Su Chen FAN ,  Dechao GUO ,  Carl RADENS ,  Indira SESHADRI

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/7682 ,  H01L21/76849 ,  H01L21/76877

Abstract: An interconnect layer for a device and methods for fabricating the interconnect layer are provided. The interconnect layer includes first metal structures arranged in a first array in the interconnect layer and second metal structures, arranged in a second array in the interconnect layer. The second array includes at least one metal structure positioned between two metal structures of the first metal structures. The interconnect layer also includes a spacer material formed around each of the first metal structures and the second metal structures and air gaps formed in the spacer material on each side of the first metal structures.

公开(公告)号：US11678480B2

公开(公告)日：2023-06-13

申请号：US17537955

申请日：2021-11-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/532

CPC classification number: H10B12/485 ,  H01L21/7682 ,  H01L23/5329 ,  H10B12/053 ,  H10B12/34 ,  H01L2221/1047

Abstract: The present application discloses a method for fabricating the semiconductor device with the porous decoupling features. The method includes providing a substrate; integrally forming a first conductive line and a bottom contact on the substrate; integrally forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact; and forming a porous insulating layer between the first conductive line spacer and the bottom contact spacer.

公开(公告)号：US11670504B2

公开(公告)日：2023-06-06

申请号：US16419426

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Andrew J. Brown ,  Dilan Seneviratne

IPC: H01L21/02 ,  H01L23/532 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L21/02345 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02194 ,  H01L21/76825 ,  H01L21/76841 ,  H01L23/5329 ,  H01L23/53228 ,  H01L28/60

Abstract: A thin-film insulator comprises a first electrode over a substrate. A photo up-converting material is over the first electrode. A cured photo-imageable dielectric (PID) containing a high-k filler material is over the photo up-converting material, wherein the cured PID is less than 4 μm in thickness, and a second electrode is over the cured PID.