公开(公告)号：US20170366612A1

公开(公告)日：2017-12-21

申请号：US15597550

申请日：2017-05-17

Applicant: FUJITSU LIMITED

Inventor： Masahiko Yamada ,  Tsuyoshi HASHIMOTO

IPC: H04L29/08 ,  G06F12/0813 ,  H04L29/06

CPC classification number: H04L67/1097 ,  G06F12/0813 ,  G06F2212/1016 ,  G06F2212/154 ,  G06F2212/60 ,  G06F2212/62 ,  H04L67/2852 ,  H04L67/2885 ,  H04L67/40 ,  H04L67/42

Abstract: A memory cache control method for a parallel processing device having a plurality of nodes, wherein a first node stores first data as a client cache in a first storage device and switches an use of the stored first data to a server cache; and a second node stores the first data in a second storage device which is slower than the first storage device, records data management information which indicates that the first data is being stored by in the first storage device of the first node, and when a transmission request of the first data is received from a third node, refers to the data management information, and when the first data is stored in the first storage device of the first node and when the first data is switched to the server cache, instructs the first node to transmit the first data to the third node.

公开(公告)号：US09836401B2

公开(公告)日：2017-12-05

申请号：US15222940

申请日：2016-07-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Jin Lee ,  Kyung Jin Byun ,  Nak Woong Eum

IPC: G06F12/08 ,  G06F12/084 ,  G06F9/30 ,  G06F12/0842 ,  G06F12/0875

CPC classification number: G06F12/084 ,  G06F9/3017 ,  G06F12/0842 ,  G06F12/0875 ,  G06F17/5022 ,  G06F2212/452 ,  G06F2212/62 ,  G06F2217/68

Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.

公开(公告)号：US09812221B1

公开(公告)日：2017-11-07

申请号：US14849390

申请日：2015-09-09

Applicant: John L. Hagen ,  David J. Radack ,  Lloyd F. Aquino ,  Todd E. Miller

Inventor： John L. Hagen ,  David J. Radack ,  Lloyd F. Aquino ,  Todd E. Miller

IPC: G06F12/08 ,  G11C29/38 ,  G11C29/36 ,  G06F12/0891 ,  G06F12/0815

CPC classification number: G11C29/38 ,  G06F12/0815 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/50 ,  G06F2212/62 ,  G06F2212/682 ,  G11C5/14 ,  G11C29/36

Abstract: A system and method for verifying cache coherency in a safety-critical avionics processing environment includes a multi-core processor (MCP) having multiple cores, each core having at least an L1 data cache. The MCP may include a shared L2 cache. The MCP may designate one core as primary and the remainder as secondary. The primary core and secondary cores create valid TLB mappings to a data page in system memory and lock L1 cache lines in their data caches. The primary core locks an L2 cache line in the shared cache and updates its locked L1 cache line. When notified of the update, the secondary cores check the test pattern received from the primary core with the updated test pattern in their own L1 cache lines. If the patterns match, the test passes; the MCP may continue the testing process by updating the primary and secondary statuses of each core.

公开(公告)号：US09811281B2

公开(公告)日：2017-11-07

申请号：US15092699

申请日：2016-04-07

Applicant: International Business Machines Corporation

Inventor： John Alan Bivens ,  Koushik K. Das ,  Min Li ,  Ruchi Mahindru ,  Harigovind V. Ramasamy ,  Yaoping Ruan ,  Valentina Salapura ,  Eugen Schenfeld

IPC: G06F12/00 ,  G06F12/08 ,  G06F3/06 ,  G06F12/0808

CPC classification number: G06F3/0631 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0641 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F11/1446 ,  G06F11/1453 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0806 ,  G06F12/0808 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/502 ,  G06F2212/62

Abstract: A memory management service occupies a configurable portion of an overall memory system in a disaggregate compute environment. The service provides optimized data organization capabilities over the pool of real memory accessible to the system. The service enables various types of data stores to be implemented in hardware, including at a data structure level. Storage capacity conservation is enabled through the creation and management of high-performance, re-usable data structure implementations across the memory pool, and then using analytics (e.g., multi-tenant similarity and duplicate detection) to determine when data organizations should be used. The service also may re-align memory to different data structures that may be more efficient given data usage and distribution patterns. The service also advantageously manages automated backups efficiently.

公开(公告)号：US20170300298A1

公开(公告)日：2017-10-19

申请号：US15458074

申请日：2017-03-14

Applicant: FUJITSU LIMITED

Inventor： Hiroyuki Ishii

IPC: G06F7/38 ,  G06F12/08

CPC classification number: G06F7/38 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0842 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/62

Abstract: An arithmetic processing device includes arithmetic processing cores, and a control circuit that includes a request port accepting a request for a memory space; a processing circuit unit that executes processing of the request; a control pipeline that determines whether or not the processing is executable by the processing circuit unit on the request input through the request port, and that executes first abort processing for the request when the processing is not executable on the request, and issues the processing to the processing circuit unit when the processing is executable; and an identical-address request arbitration circuit that holds an occurrence order of requests with an identical address that is aborted due to the processing being not executable, and that executes second abort processing on those of requests input to the control pipeline which have the identical address and which are other than a leading request in the occurrence order.

公开(公告)号：US09792217B2

公开(公告)日：2017-10-17

申请号：US15007992

申请日：2016-01-27

Applicant: Dell Products L.P.

Inventor： Farzad Khosrowpour ,  Steven Hunt

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0813 ,  G06F12/0804 ,  G06F12/0866

CPC classification number: G06F12/0893 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0866 ,  G06F2212/154 ,  G06F2212/604 ,  G06F2212/62

Abstract: Methods and systems for normalizing a read-write cache allocation pool for virtual desktop infrastructure (VDI) workloads are disclosed. The method includes determining a cache allocation policy; determining a range of expected input/output (I/O) levels of a storage system; determining a current I/O level of the storage system; determining a target cache allocation based on the cache allocation policy, the range of expected I/O levels, and the current I/O level, the target cache allocation including a first memory region allocated to read cache operations and a second memory region allocated to write cache operations; and reallocating cache memory based on the target cache allocation.

公开(公告)号：US09785568B2

公开(公告)日：2017-10-10

申请号：US14715114

申请日：2015-05-18

Applicant: Empire Technology Development LLC

Inventor： Sriram Vajapeyam

IPC: G06F12/08 ,  G06F12/0897 ,  G06F12/0888 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0831 ,  G06F12/0808

CPC classification number: G06F12/0897 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/314 ,  G06F2212/6046 ,  G06F2212/62 ,  Y02D10/13

Abstract: Techniques described herein are generally related to retrieval of data in computer systems having multi-level caches. The multi-level cache may include at least a first cache and a second cache. The first cache may be configured to receive a request for a cache line. The request may be associated with an instruction executing on a tile of the computer system. A suppression status of the instruction may be determined by a first cache controller to determine whether look-up of the first cache is suppressed based upon the determined suppression status. The request for the cache line may be forwarded to the second cache by the first cache controller after the look-up of the first cache is suppressed.

公开(公告)号：US20170286303A1

公开(公告)日：2017-10-05

申请号：US15087649

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Khary Jason ALEXANDER ,  Eric Francis ROBINSON

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6022 ,  G06F2212/62

Abstract: Systems and methods relate to servicing a demand miss for a cache line in a first cache (e.g., an L1 cache) of a processing system, for example, when none of one or more fill buffers for servicing the demand miss are available. In exemplary aspects, the demand miss is converted to a prefetch operation to prefetch the cache line into a second cache (e.g., an L2 cache), wherein the second cache is a backing storage location for the first cache. Thus, servicing the demand miss is not delayed until a fill buffer becomes available, and once a fill buffer becomes available, the prefetched cache line is returned from the second cache to the available fill buffer.

公开(公告)号：US20170277447A1

公开(公告)日：2017-09-28

申请号：US15508866

申请日：2015-09-28

Applicant: Agency For Science, Technology And Research

Inventor： Weiya XI ,  Chao JIN ,  Khai Leong YONG ,  Pantelis ALEXOPOULOS

IPC: G06F3/06 ,  G06F12/0811

CPC classification number: G06F3/0613 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0671 ,  G06F3/0683 ,  G06F3/0685 ,  G06F12/0238 ,  G06F12/0811 ,  G06F2212/62

Abstract: A printed circuit board assembly (PCBA) for a storage device comprising a non-volatile memory (NVM) and a multi-core processor, wherein a first core of the multi-core processor is devoted to external interface management and a second core of the multi-core processor is devoted to internal data management.

公开(公告)号：US09772678B2

公开(公告)日：2017-09-26

申请号：US15139455

申请日：2016-04-27

Applicant: Intel Corporation

Inventor： Ruchira Sasanka ,  Alexander Gendler ,  Udi Sherel

IPC: G06F1/32 ,  G06F1/26 ,  G06F12/02 ,  G06F12/084

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F1/324 ,  G06F12/0223 ,  G06F12/084 ,  G06F2212/62 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.