公开(公告)号：US5994734A

公开(公告)日：1999-11-30

申请号：US120490

申请日：1998-07-21

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L29/511

Abstract: A modified gate structure for a non-volatile memory device is formed over a substrate. The modified gate structure from bottom to top comprises a first dielectric layer, a first conductive layer, a second dielectric layer formed on said first conductive layer, a third dielectric layer, a refractory metal layer, and a second conductive layer. The third dielectric layer is made of tantalum oxide or BST, and the refractory metal layer can be made of tungsten, platinum, titanium, molybdenum, and tantalum.

Abstract translation: 用于非易失性存储器件的修改的栅极结构形成在衬底上。 从底部到顶部的修改的栅极结构包括第一介电层，第一导电层，形成在所述第一导电层上的第二介电层，第三介电层，难熔金属层和第二导电层。 第三电介质层由氧化钽或BST制成，难熔金属层可以由钨，铂，钛，钼和钽制成。

公开(公告)号：US5985715A

公开(公告)日：1999-11-16

申请号：US40259

申请日：1998-03-17

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A method of fabricating a stacked type capacitor. A semiconductor substrate having a transistor, a field oxide layer, and a conductive layer formed on top of the field oxide layer is provided. The transistor comprises a gate and a source/drain region. A first dielectric layer is formed over the substrate. An oxide layer is formed over the first dielectric layer. A second dielectric layer is formed on the oxide layer. An etching step is performed to the second dielectric layer to form an opening therein. A first poly-silicon layer is formed on the second dielectric layer and the opening. The first poly-silicon layer is etched back to remove a part of the first poly-silicon layer. A first spacer is formed on a wall of the opening. The oxide layer is etched for a first height by using the first spacer and the second dielectric layer as a first mask. A second poly-silicon layer is formed on the second dielectric layer and the opening. An etching back is performed to the second poly-silicon layer to remove a part of the second poly-silicon layer. A second spacer is formed on a wall of the first height in the opening. The oxide layer is etched for a second height by using the first spacer, the second spacer, and the second dielectric layer as a second mask, and a third spacer is formed. The first dielectric layer is formed to expose the source/drain region. Selective epitaxy growth is performed to form an epitaxy layer on the first spacer, the second spacer, and the third spacer. The second dielectric layer and the oxide layer are removed to form a bottom electrode. A third dielectric layer is formed on the bottom electrode. A top electrode is formed on the third dielectric layer.

Abstract translation: 一种叠层型电容器的制造方法。 提供了具有形成在场氧化物层顶部上的晶体管，场氧化物层和导电层的半导体衬底。 晶体管包括栅极和源极/漏极区域。 第一电介质层形成在衬底上。 在第一电介质层上形成氧化物层。 在氧化物层上形成第二电介质层。 对第二电介质层进行蚀刻步骤以在其中形成开口。 在第二电介质层和开口上形成第一多晶硅层。 将第一多晶硅层回蚀刻以去除第一多晶硅层的一部分。 第一间隔件形成在开口的壁上。 通过使用第一间隔物和第二介电层作为第一掩模，氧化物层被蚀刻第一高度。 在第二电介质层和开口上形成第二多晶硅层。 对第二多晶硅层进行蚀刻以去除第二多晶硅层的一部分。 第二间隔件形成在开口中的第一高度的壁上。 通过使用第一间隔物，第二间隔物和第二电介质层作为第二掩模，氧化物层被蚀刻第二高度，并且形成第三间隔物。 形成第一电介质层以暴露源极/漏极区域。 进行选择性外延生长以在第一间隔物，第二间隔物和第三间隔物上形成外延层。 去除第二电介质层和氧化物层以形成底部电极。 在底部电极上形成第三电介质层。 顶电极形成在第三电介质层上。