公开(公告)号：US20030189050A1

公开(公告)日：2003-10-09

申请号：US10116342

申请日：2002-04-03

Inventor： Harry H. Fite

IPC: B65D041/04

CPC classification number: H03K19/1733 ,  F17C13/002 ,  F17C13/005 ,  F17C2201/0109 ,  F17C2201/0119 ,  F17C2201/032 ,  F17C2201/058 ,  F17C2205/0308 ,  F17C2260/015 ,  F17C2270/0745

Abstract: A cylinder cap system for decreasing the amount of time required to remove and install a protective cap upon a gas cylinder. The cylinder cap system includes a cap member having a lower portion, a middle portion, an upper portion and a lower threaded opening, and a receiver member positioned concentrically within the upper portion for receiving a drive shaft of a ratchet tool. The receiver member is comprised of a floor and a plurality of inner walls forming a polygonal shaped structure for receiving a tool such as an allen wrench. A detent cavity is preferably positioned within an inner surface of the inner walls for catchably receiving a detent ball of the drive shaft of the tool.

Abstract translation: 气缸盖系统，用于减少在气瓶上拆卸和安装保护盖所需的时间。 气缸盖系统包括具有下部分，中间部分，上部分和下部螺纹开口的帽部件，以及同心地定位在上部部分内用于容纳棘轮工具的驱动轴的接收部件。 接收器构件包括形成多边形结构的地板和多个内壁，用于接收诸如内六角扳手的工具。 止动腔优选地定位在内壁的内表面内，用于可收容地容纳工具的驱动轴的止动球。

公开(公告)号：US06515504B1

公开(公告)日：2003-02-04

申请号：US09454953

申请日：1999-12-03

Applicant: Fernando Incertis Carro

Inventor： Fernando Incertis Carro

IPC: H03K19177

CPC classification number: H03K19/096 ,  H03K19/1733

Abstract: In a data processing system, a circuit and methods for carrying out sequential logic functions are disclosed aimed at overcoming the problems encountered with the standard approach for designing synchronous logic, timed from a single clock source. When propagation delays through logic elements and their interconnections are becoming of the same order of magnitude as the clock period necessary to achieve the required level of performance of a logic function, the distribution of a common timing reference or clock over an entire function is becoming the limiting factor. In a complete departure from the standard approach, logic functions of the invention are capable of supplying their own timing information to their interface thus, self asserting their result and capable of requesting new set of inputs when needed. Therefore, logic functions of the invention are autonomous and do not rely on the distribution of a clock to operate.

Abstract translation: 在数据处理系统中，公开了用于执行顺序逻辑功能的电路和方法，其目的是克服用于设计从单个时钟源定时的同步逻辑的标准方法遇到的问题。 当通过逻辑元件及其互连的传播延迟变得与实现逻辑功能的所需性能水平所需的时钟周期相同的数量级时，公共定时参考或时钟在整个功能上的分布正在成为 限制因素。 完全脱离标准方法，本发明的逻辑功能能够将它们自己的定时信息提供给它们的接口，从而自我确定其结果并且能够在需要时请求新的一组输入。 因此，本发明的逻辑功能是自主的，不依赖于时钟的分配来操作。

公开(公告)号：US6078196A

公开(公告)日：2000-06-20

申请号：US932751

申请日：1997-09-17

Applicant: Eric S. Gayles

Inventor： Eric S. Gayles

IPC: H03K19/096 ,  H03K19/173 ,  H03K19/094 ,  H03K19/00 ,  H03K19/20

CPC classification number: H03K19/1733 ,  H03K19/0963

Abstract: Data enabled complex logic gates provide improved speed/power performance over conventional topologies such as static logic or clocked domino logic. Within a data enabled complex logic gate, complementary parallel logic structures, such as NFET logic trees, are configured such that for any combination of input variables one logic structure will produce a logic low as an output and the other logic structure will produce a logic high as an output. The logic structures are cross-coupled to each other by way of internal precharge devices, and are further individually coupled to an output latch. In this way the logic structures can be precharged to prepare for evaluation of the next set of input signals while the output latch maintains the result of the previous evaluation. In a further aspect of the invention, data enabled complex logic gates are combined with pass gate latches and multiplexer based logic gates to produce a high-speed, low-power logic pipeline.

Abstract translation: 数据启用的复杂逻辑门提供了比常规拓扑（例如静态逻辑或时钟多米诺逻辑）更高的速度/功率性能。 在启用数据的复杂逻辑门中，配置了诸如NFET逻辑树之类的互补并行逻辑结构，使得对于输入变量的任何组合，一个逻辑结构将产生作为输出的逻辑低，而另一逻辑结构将产生逻辑高 作为输出。 逻辑结构通过内部预充电装置彼此交叉耦合，并进一步单独地耦合到输出锁存器。 以这种方式，逻辑结构可以被预先充电以准备评估下一组输入信号，同时输出锁存器保持先前评估的结果。 在本发明的另一方面，数据使能的复杂逻辑门与传输门锁存器和基于复用器的逻辑门相结合以产生高速，低功率逻辑管线。

公开(公告)号：US5896308A

公开(公告)日：1999-04-20

申请号：US653957

申请日：1996-05-22

Applicant: Christine Gonfaus ,  Jacky Lebrun

Inventor： Christine Gonfaus ,  Jacky Lebrun

IPC: G06F7/50 ,  G06F7/501 ,  H03K19/0948 ,  H03K19/173

CPC classification number: G06F7/501 ,  H03K19/0948 ,  H03K19/1733

Abstract: The present invention relates to a combinational logic circuit including at least a pair of inputs and an output line; at least a first module and a symmetrical module; the first module including a parallel cell and a series cell; the parallel cell including two switches controlled by the pair of inputs and in parallel between a supply terminal and an output terminal coupled with the output line; the series cell including two switches controlled by the pair of inputs and in series between the supply and the output line; the symmetrical module including two cells symmetrical to the cells of the first module, with respect to the output line, coupled with a second supply and controlled in phase opposition.

Abstract translation: 本发明涉及至少包括一对输入和输出线的组合逻辑电路; 至少第一模块和对称模块; 所述第一模块包括并行单元和串联单元; 所述并联单元包括由所述一对输入控制的两个开关，并且并联在供电端子和与所述输出线耦合的输出端子之间; 所述串联电池包括由所述一对输入控制并且在所述电源和所述输出线之间串联的两个开关; 对称模块包括与第一模块的单元相对于输出线对称的两个单元，与第二电源和受控的相位相反。

公开(公告)号：US5023486A

公开(公告)日：1991-06-11

申请号：US502221

申请日：1990-03-30

Applicant: Geoffrey S. Gongwer

Inventor： Geoffrey S. Gongwer

IPC: H03K3/037 ,  H03K3/356 ,  H03K19/0175 ,  H03K19/173

CPC classification number: H03K3/037 ,  H03K19/1733 ,  H03K3/35606

Abstract: A logic output control circuit for selecting between stored and nonstored outputs from a data input and a clock having a data pass gate MOS transistor receiving a logic signal at its data input and either blocking the signal or passing it to a cross-coupled inverter gate latch depending on a control signal at its control gate terminal. The control signal is derived in one embodiment by a logic gate with a programming signal input, a clock input and a control signal output, and in a second embodiment by a set of pass gate transistors respectively receiving a clock signal and a fixed level signal and controlled by a programming signal. When the programming signal has one logic level, the data pass transistor is always on and the logic signal flows continually to the output. When the programming signal has the other logic level, the data pass transistor switches on and off with the clock signal and the circuit operates as a latch. The clock signal may be an input clock or a pulsed clock which is an edge triggered version of the pin clock signal.

公开(公告)号：US4797569A

公开(公告)日：1989-01-10

申请号：US114546

申请日：1987-10-28

Applicant: Ziya G. Boyacigiller

Inventor： Ziya G. Boyacigiller

IPC: G01R19/165 ,  H03K19/173 ,  H03K5/24 ,  G05F1/46 ,  H03K3/01

CPC classification number: G01R19/165 ,  H03K19/1732 ,  H03K19/1733

Abstract: An integrateable circuit is disclosed which allows selection between pre-defined and user-defined characteristics. The circuit utilizes a single input terminal for both selection and definition by a user. In a preferred embodiment, a comparator senses whether a user-supplied voltage at this input terminal is at a logic low level or not. If the voltage at this input terminal is at a logic level low, an internal voltage proportional to a pre-defined characteristic is enabled. If the voltage at this input terminal is not at a logic low level, the internal voltage proportional to the pre-defined characteristic is disconnected and a characteristic defined by the user, its value proportional to the user-supplied voltage present at the input terminal, is connected and activated.

Abstract translation: 公开了可以在预定义和用户定义的特征之间进行选择的可集成电路。 该电路利用单个输入端子进行用户的选择和定义。 在优选实施例中，比较器检测该输入端的用户提供的电压是否处于逻辑低电平。 如果该输入端子处的电压处于逻辑电平低电平，则与预定义特性成比例的内部电压被使能。 如果该输入端子的电压不在逻辑低电平，则与预定义特性成比例的内部电压被断开，用户定义的特性与输入端子上存在的用户供电电压成比例， 已连接并激活。

公开(公告)号：US4758985A

公开(公告)日：1988-07-19

申请号：US845287

申请日：1986-03-28

Applicant: William S. Carter

Inventor： William S. Carter

IPC: G11C19/28 ,  H03K3/037 ,  H03K5/1534 ,  H03K19/173 ,  G11C13/00

CPC classification number: G11C19/282 ,  H03K19/1733 ,  H03K19/1736 ,  H03K3/037 ,  H03K5/1534

Abstract: A microprocessor controlled configurable logic circuit achieves versatility by including a configurable combinational logic element, a configurable storage circuit, a configurable status buffer, and a configurable output select logic. The input signals to the configurable combinational logic element are input signals to the configurable logic circuit and feedback signals from the storage circuit. The storage circuit may be configured to operate as a D flip-flop with or without set and reset inputs, or as an edge detector. In conjunction with the combinational logic element, the storage circuit may also operate as a stage of a shift register or counter. The output select logic selects output from among the output signals of the combinational logic element and the storage circuit. The configurable status buffer may be configured to provide status information on selected important internal signals of the configurable logic circuit. A microprocessor interface structure may access an array of these configurable logic circuits through the status buffer to read different internal output signals from different circuits in the array. Providing separate input and output to a microprocessor leaves the storage element free for other uses and does not require the logic provided by the logic elements.

Abstract translation: 微处理器控制的可配置逻辑电路通过包括可配置组合逻辑元件，可配置存储电路，可配置状态缓冲器和可配置输出选择逻辑来实现多功能性。 到可配置组合逻辑元件的输入信号是到可配置逻辑电路的输入信号和来自存储电路的反馈信号。 存储电路可以被配置为作为具有或不具有设置和复位输入的D触发器或作为边缘检测器来操作。 结合组合逻辑元件，存储电路也可以作为移位寄存器或计数器的级进行操作。 输出选择逻辑从组合逻辑元件和存储电路的输出信号中选择输出。 可配置状态缓冲器可以被配置为提供关于可配置逻辑电路的选择的重要内部信号的状态信息。 微处理器接口结构可以通过状态缓冲器访问这些可配置逻辑电路的阵列，以从阵列中的不同电路读取不同的内部输出信号。 向微处理器提供单独的输入和输出使存储元件免于其他用途，并且不需要由逻辑元件提供的逻辑。

公开(公告)号：US4710898A

公开(公告)日：1987-12-01

申请号：US716388

申请日：1985-03-27

Applicant: Masahiko Sumi

Inventor： Masahiko Sumi

IPC: H03K19/173 ,  H03K19/177 ,  G11C13/00

CPC classification number: H03K19/17712 ,  H03K19/1733

Abstract: An apparatus for performing a desired logical function comprises a logic circuit including signal lines, a storage device storing information which determines whether each of the signal lines is to be sensitized or desensitized, and a device for selectively sensitizing or desensitizing the signal lines on the basis of the information stored in the storage device. The apparatus can be repeatedly and easily programmed by altering information stored in the storage device. Moreover, it can be formed as a highly integrated circuit.

Abstract translation: 用于执行期望的逻辑功能的装置包括逻辑电路，该逻辑电路包括信号线，存储装置，该存储装置存储确定每个信号线是否被增感或脱敏的信息，以及用于在该基础上选择性地使信号线敏感或脱敏的装置 存储在存储设备中的信息。 可以通过改变存储在存储装置中的信息来重复且容易地编程该装置。 此外，它可以形成为高度集成的电路。

公开(公告)号：US4605872A

公开(公告)日：1986-08-12

申请号：US558455

申请日：1983-12-06

Applicant: Robert D. Rung

Inventor： Robert D. Rung

IPC: G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L27/10 ,  H03K17/567 ,  H03K19/173 ,  H03K17/12

CPC classification number: G11C29/785 ,  H03K17/567 ,  H03K19/1733

Abstract: A programmable circuit is described which is particularly well suited for programming or customizing redundant elements in CMOS integrated circuits. This programmable circuit, which is formed on a semiconductor substrate together with a redundant semiconductor device, uses a parasitic switching device on the semiconductor substrate to deselect the redundant semiconductor device in response to a programming signal. The programmable circuit includes an input terminal to receive the programming signal, a parasitic SCR formed on the semiconductor substrate and coupled to the input terminal and a deselect device such as a fuse or antifuse to deselect the redundant semiconductor device. The parasitic SCR is actuated in response to the programming signal and the deselect device is connected to the SCR and the semiconductor device to deselect the semiconductor device from the redundant electrical circuit in response to the actuation of the SCR by the programming signal.

Abstract translation: 描述了一种可编程电路，其特别适用于编程或定制CMOS集成电路中的冗余元件。 与冗余半导体器件一起形成在半导体衬底上的该可编程电路使用半导体衬底上的寄生开关器件来响应于编程信号来取消选择冗余半导体器件。 可编程电路包括用于接收编程信号的输入端子，形成在半导体衬底上并耦合到输入端子的寄生SCR和诸如熔丝或反熔丝的取消选择器件以取消选择冗余半导体器件。 寄生SCR响应于编程信号被致动，并且取消选择装置连接到SCR和半导体器件，以响应于编程信号对SCR的致动而从冗余电路中取消半导体器件。

公开(公告)号：US4541071A

公开(公告)日：1985-09-10

申请号：US514900

申请日：1983-07-18

Applicant: Kenji Ohmori

Inventor： Kenji Ohmori

IPC: G06F7/00 ,  G06F7/76 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177 ,  G06F7/04 ,  G06F13/00

CPC classification number: G06F7/76 ,  G06F17/5022 ,  H03K19/1733 ,  H03K19/17704

Abstract: A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.

Abstract translation: 门组件被仿真为逻辑组，它们分别依次检查相应逻辑组的输入信号以提供其输出信号。 解码存储器（24）预先加载解码图案。 一对解码图案定义了对于每个逻辑组输入信号的逻辑信号对而为每个门预先确定的一对可变组。 在门存储器单元（25）中，可变对被执行为门确定的逻辑运算以提供逻辑组输出信号的逻辑信号。 首先，寄存器组（15）装载有组件的输入信号。 之后，寄存器组装入每个逻辑组的输出信号，该输出信号在下一个后续步骤中用作另一个逻辑组的输入信号。 优选地，每个逻辑组输入信号由八个逻辑信号给出。 在这种情况下，每个逻辑信号可以被给定为逻辑1和/或零状态的排列，数量为16。