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公开(公告)号：US20170352410A1
公开(公告)日：2017-12-07
申请号：US15645130
申请日：2017-07-10
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro
CPC classification number: G11C13/003 , G06F3/061 , G06F3/0658 , G06F3/0673 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2013/0088 , G11C2213/15 , G11C2213/71 , G11C2213/77
Abstract: Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first selected column and a first selected row and a second memory cell disposed between a second selected column different from the first selected column and a second selected row different from the first selected row. Accessing in parallel includes simultaneously applying access biases between the first selected column and the first selected row and between the second selected column and the second selected row. The accessing in parallel is conducted while the cells are in a thresholded condition or while the cells are in a post-threshold recovery period.
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公开(公告)号：US20170345498A1
公开(公告)日：2017-11-30
申请号：US15676560
申请日：2017-08-14
Applicant: Micron Technology, Inc.
Inventor： DerChang Kau , Gianpaolo Spadini
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0097 , G11C16/08 , G11C16/24 , H01L23/528 , H01L27/2427 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144 , H01L2924/0002 , H01L2924/00
Abstract: Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
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公开(公告)号：US20170345491A1
公开(公告)日：2017-11-30
申请号：US15163801
申请日：2016-05-25
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： Anirban ROY , Michael A. SADD
CPC classification number: G11C13/004 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/005 , G11C11/1659 , G11C11/1673 , G11C11/2259 , G11C11/2273 , G11C13/0023 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C29/52 , G11C2213/78 , G11C2213/79 , G11C2213/82
Abstract: An integrated circuit includes a first plurality of flip flops; a first bank of resistive memory cells, wherein each flip flop of the first plurality of flip flops uniquely corresponds to a resistive memory cell of the first bank of resistive memory cells; write circuitry configured to store data from the first plurality of flip flops to the first bank of resistive memory cells; and read circuitry configured to read data from the first bank of resistive memory cells and provide the data from the first bank for storage into the first plurality of flip flops.
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公开(公告)号：US20170323681A1
公开(公告)日：2017-11-09
申请号：US15596499
申请日：2017-05-16
Applicant: UNITY SEMICONDUCTOR CORPORATION
Inventor： Chang Hua Siau , Bruce Lynn Bateman
CPC classification number: G11C5/06 , G11C5/08 , G11C7/00 , G11C7/04 , G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0023 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C16/24 , G11C2213/71
Abstract: A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element. The global bit line and/or the selected local bit line can be biased to compensate for the Process Voltage Temperature (PVT) variation.
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公开(公告)号：US09812197B2
公开(公告)日：2017-11-07
申请号：US15316060
申请日：2014-10-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Luke Whitaker
CPC classification number: G11C13/004 , G11C11/1673 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C2207/002
Abstract: One example provides a device including a first transistor having a source-drain path electrically coupled between a first node and a second node. The device includes an operational amplifier having an output electrically coupled to a gate of the first transistor. The operational amplifier controls the first transistor to maintain a predetermined voltage on the first node. A first current source adds a current at the first node and a second current source subtracts the current at the second node.
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公开(公告)号：US20170316827A1
公开(公告)日：2017-11-02
申请号：US15521542
申请日：2014-10-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning GE , Jianhua YANG , John Paul STRACHAN , Miao HU
CPC classification number: G11C13/0069 , G06F17/11 , G06F17/16 , G06G7/16 , G11C7/1006 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/77
Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.
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公开(公告)号：US09747978B2
公开(公告)日：2017-08-29
申请号：US14850152
申请日：2015-09-10
Applicant: Intel Corporation
Inventor： Balaji Srinivasan , Doyle Rivers , Derchang Kau , Matthew Goldman
CPC classification number: G11C13/0004 , G11C7/12 , G11C8/08 , G11C11/24 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2013/0057 , G11C2213/77
Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.
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公开(公告)号：US09741766B2
公开(公告)日：2017-08-22
申请号：US15152342
申请日：2016-05-11
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor： Kenichi Murooka
CPC classification number: H01L27/2481 , G11C5/02 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/78 , H01L21/768 , H01L27/2454 , H01L29/66666 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608
Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
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公开(公告)号：US20170236582A1
公开(公告)日：2017-08-17
申请号：US15583476
申请日：2017-05-01
Applicant: SK hynix Inc.
Inventor： Jung Hyuk YOON , Yoon Jae SHIN
CPC classification number: G11C13/0028 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C13/0002 , G11C13/0023 , G11C13/0038 , G11C13/004 , G11C13/0069
Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
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公开(公告)号：US20170229171A1
公开(公告)日：2017-08-10
申请号：US15328269
申请日：2014-11-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Phillip David Misek , Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/0023 , G11C13/0021 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C16/06 , G11C16/10 , G11C2013/0073 , G11C2213/77 , G11C2213/79
Abstract: Example implementations relate to memory array drivers. For example, a memory array includes a memory cell. The memory array also includes a bit line coupled to the memory cell and a word line coupled to the memory cell. The memory array further includes a first memory array driver having a first terminal and a second terminal. The first terminal is coupled to the bit line. The second terminal is coupled to the word line. The memory array further includes a second memory array driver having a third terminal and a fourth terminal. The third terminal is coupled to the bit line. The fourth terminal is coupled to the word line.
