-
公开(公告)号：US10002872B2
公开(公告)日：2018-06-19
申请号：US15488489
申请日：2017-04-16
Applicant: ChengDu HaiCun IP Technology LLC
Inventor： Guobiao Zhang
IPC: H01L27/10 , G11C17/16 , H01L23/525
CPC classification number: H01L27/10 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2013/0045 , G11C2213/15 , G11C2213/71 , G11C2213/73 , H01L23/5252 , H01L27/0688 , H01L27/101 , H01L27/11206
Abstract: The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTPV). It comprises a plurality of vertical OTP strings formed side-by-side on a substrate circuit. Each OTP string comprises a plurality of vertically stacked OTP cells. Each OTP cell comprises an antifuse layer. The horizontal address lines and the vertical address lines comprise oppositely-doped semiconductor materials.
-
公开(公告)号：US20180166114A1
公开(公告)日：2018-06-14
申请号：US15894737
申请日：2018-02-12
Applicant: SK hynix Inc.
Inventor： Jae-Yun Yi , Sung-Woong Chung , Seok-Pyo Song
CPC classification number: G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , H01L43/08
Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a bit line; a source line; a plurality of resistive memory cells among which a selected memory cell forms a current path between the bit line and the source line; a read current supply unit configured to supply read current to the bit line in a read operation; a sense amplifier configured to generate read data in response to a voltage level of the bit line in the read operation; and a variable switch element configured to flow current from the source line to a ground terminal in the read operation, and be decreased in its resistance value as a voltage level of the source line is high.
-
公开(公告)号：US20180159033A1
公开(公告)日：2018-06-07
申请号：US15890296
申请日：2018-02-06
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Ming-Che Wu , Tanmay Kumar
CPC classification number: H01L45/146 , G11C11/5685 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/147 , H01L45/1608
Abstract: Systems and methods for providing a Barrier Modulated Cell (BMC) structure that may comprise a reversible resistance-switching memory element within a memory array are described. The BMC structure may include a barrier layer comprising a layer of amorphous germanium or amorphous silicon germanium paired with a conductive metal oxide, such as titanium dioxide (TiO2), strontium titanate (SrTiO3), or a binary metal oxide. The BMC structure may include a conductive metal oxide in series with an amorphous layer of a low bandgap material. The low bandgap material may comprise a semiconductor material with a bandgap energy (Eg) less than 1.0 eV. The improved BMC structure may be used for providing multi-level memory elements within a three dimensional memory array.
-
公开(公告)号：US20180158523A1
公开(公告)日：2018-06-07
申请号：US15704995
申请日：2017-09-14
Applicant: SK hynix Inc.
Inventor： Kwang-Myoung Rho
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1673 , G11C11/1693 , G11C13/0007 , G11C13/0061 , G11C2013/0042 , G11C2013/0045 , G11C2013/0054 , G11C2207/002
Abstract: An electronic device includes a semiconductor memory that includes: resistive storage cells; a reference resistance cell; a comparison block electrically coupled to the resistive storage cells and the reference resistance cell through first and second input terminals, to compare a cell current flowing through the first input terminal and a reference current flowing through the second input terminal; a first clamp part to control a maximum current amount of the cell current depending on a voltage level of a first node; a second clamp part to control a maximum current amount of the reference current depending on the voltage level of the first node; a voltage stabilization block to stabilize a voltage of the first node during a charging or a discharging period; and a switching part electrically coupled with the first node and the voltage stabilization block in the charging period or the discharging period.
-
公开(公告)号：US09991265B2
公开(公告)日：2018-06-05
申请号：US15157565
申请日：2016-05-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato
IPC: H01L27/11 , H01L27/105 , H01L27/108 , H01L27/11551 , H01L27/1156 , H01L27/12 , H01L29/24 , H01L29/786 , G11C13/00 , H01L49/02
CPC classification number: H01L27/1052 , G11C13/0007 , G11C13/003 , G11C2213/79 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/11551 , H01L27/1156 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L28/40 , H01L29/24 , H01L29/7869 , H01L29/78696
Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.
-
公开(公告)号：US09978450B2
公开(公告)日：2018-05-22
申请号：US15810400
申请日：2017-11-13
Applicant: Zeno Semiconductor, Inc.
Inventor： Yuniarto Widjaja
IPC: G11C11/00 , G11C14/00 , G11C13/00 , H01L45/00 , G11C11/56 , G11C11/4074 , G11C11/402 , H01L27/108 , H01L27/102 , H01L27/105 , H01L29/788 , H01L29/78 , H01L29/66 , H01L27/24 , G11C11/404 , G11C16/04
CPC classification number: G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
-
公开(公告)号：US09966134B1
公开(公告)日：2018-05-08
申请号：US15407357
申请日：2017-01-17
Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor： Jong Hyuk Park , Sang-Soo Lee , Keun-Young Shin , Young Jin Kim , Min Park , Heesuk Kim , Jeong Gon Son , Wan Ki Bae
CPC classification number: H01L45/1253 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0016 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/11 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/16 , H01L45/1675
Abstract: Disclosed is a multilevel nonvolatile resistive random-access memory device including a lower electrode, an upper electrode, and an insulation film interposed between the lower electrode and the upper electrode. Each of the lower electrode and the upper electrode includes a plate-shaped portion, and a patterned portion formed on the plate-shaped portion, and the patterned portion includes a protruding 3-dimensional prism structure pattern in which a plurality of prism-shaped structures is repeatedly arranged at a constant interval in a given direction. The patterned portion of the lower electrode and the patterned portion of the upper electrode are arranged to face each other, and a longitudinal direction of the prism-shaped structures of the lower electrode patterned portion and a longitudinal direction of the prism-shaped structures of the upper electrode patterned portion cross each other.
-
公开(公告)号：US09966126B2
公开(公告)日：2018-05-08
申请号：US15486689
申请日：2017-04-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Oh Ahn , Sukyong Kang , Hye-Seung Yu , Jae-Hun Jung
IPC: G11C11/00 , G11C11/16 , G11C11/4076 , G11C13/00 , G06F11/10
CPC classification number: G11C11/1693 , G06F11/1004 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C11/161 , G11C11/4076 , G11C11/4093 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/0069
Abstract: A delay circuit of a semiconductor memory device includes a delay chain, a first phase converter and a second phase converter. The delay chain is connected between an input terminal and an output terminal, includes 2N delay cells, and delays a first intermediate signal to generate a second intermediate signal. The first phase converter is connected to the input terminal, and provides the first intermediate signal to the delay chain, wherein the first intermediate signal is generated by inverting a phase of an input signal or by maintaining the phase of the input signal in response to a control signal. The second phase converter is connected to the output terminal, and generates an output signal by inverting a phase of the second intermediate signal or by maintaining the phase of the second intermediate signal in response to the control signal.
-
公开(公告)号：US20180114572A1
公开(公告)日：2018-04-26
申请号：US15831059
申请日：2017-12-04
Applicant: International Business Machines Corporation
Inventor： Tayfun Gokmen , Seyoung Kim , Hyung-Min Lee , Wooram Lee , Paul Michael Solomon
IPC: G11C13/00
CPC classification number: G11C13/004 , G06N3/02 , G11C7/1006 , G11C11/54 , G11C13/0002 , G11C13/0007 , G11C13/0038 , G11C13/0069 , G11C2213/77
Abstract: A processing unit includes a circuit including a current mirror, and a capacitor providing a weight based on a charge level of the capacitor. The capacitor is charged or discharged by the current mirror.
-
公开(公告)号：US20180108403A1
公开(公告)日：2018-04-19
申请号：US15556361
申请日：2015-04-10
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , Jianhua Yang , Miao Hu , John Paul Strachan
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C7/04 , G11C13/0007 , G11C13/0033 , G11C13/0038 , G11C13/0069
Abstract: A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array.
