公开(公告)号：US06278352B1

公开(公告)日：2001-08-21

申请号：US09359892

申请日：1999-07-26

Applicant: Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

Inventor： Kuo-Ching Huang ,  Jin-Yuan Lee ,  Tse-Liang Ying

IPC: H01F500

CPC classification number: H01F5/003

Abstract: An improved thin film inductor design is described. A spiral geometry is used to which has been added a core of high permeability material located at the center of the spiral. If the high permeability material is a conductor, care must be taken to avoid any contact between the core and the spiral. If a dielectric ferromagnetic material is used, this constraint is removed from the design. Several other embodiments are shown in which, in addition to the high permeability core, provide low reluctance paths for the structure. In one case this takes the form of a frame of ferromagnetic material surrounding the spiral while in a second case it has the form of a hollow square located directly above the spiral.

Abstract translation: 描述了改进的薄膜电感器设计。 使用螺旋几何形状，其中已经添加了位于螺旋中心的高磁导率材料的核心。 如果高导磁率材料是导体，则必须注意避免芯和螺旋之间的任何接触。 如果使用介电铁磁材料，则从设计中去除该约束。 示出了其中除了高磁导率芯之外还提供用于结构的低磁阻路径的其它实施例。 在一种情况下，这采取围绕螺旋的铁磁材料框架的形式，而在第二种情况下，其具有直接位于螺旋上方的中空正方形的形式。

公开(公告)号：US06248673B1

公开(公告)日：2001-06-19

申请号：US09511334

申请日：2000-02-23

Applicant: Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

Inventor： Ji-Chung Huang ,  Jang-Cheng Hsieh ,  Chung-Cheng Wu ,  Kuo-Ching Huang

IPC: H01L21469

CPC classification number: H01L29/518 ,  H01L21/02131 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3003 ,  H01L21/31629 ,  H01L21/324 ,  Y10S438/958

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a microelectronic device. There is then formed over the microelectronic device a passivating dielectric layer formed from a passivating dielectric material selected from the group consisting of fluorosilicate glass (FSG) passivating dielectric materials, atmospheric pressure chemical vapor deposited (APCVD) passivating dielectric materials, subatmospheric pressure chemical vapor deposited (SACVD) passivating dielectric materials and spin-on-glass (SOG) passivating dielectric materials to form from the microelectronic device a passivated microelectronic device. Finally, there is then annealed thermally, while employing a thermal annealing method employing an atmosphere comprising hydrogen, the passivated microelectronic device to form a stabilized passivated microelectronic device. The method is a “pure H2 (100%)” alloy recipe to use after contact opening or metal-1 formation.

Abstract translation: 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成微电子器件。 然后在微电子器件上形成由钝化介电材料形成的钝化介电层，该钝化介电材料选自氟硅酸盐玻璃（FSG）钝化介电材料，大气压化学气相沉积（APCVD）钝化介电材料，低于大气压的化学气相沉积 （SACVD）钝化介电材料和旋涂玻璃（SOG）钝化介电材料以从微电子器件形成钝化的微电子器件。 最后，在使用采用包含氢的气氛的热退火方法的同时进行退火，该钝化微电子器件形成稳定的钝化微电子器件。 该方法是在接触开口或金属-1形成之后使用的“纯H 2（100％）”合金配方。

公开(公告)号：US6046062A

公开(公告)日：2000-04-04

申请号：US373246

申请日：1999-08-12

Applicant: Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

Inventor： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/14

Abstract: This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

Abstract translation: 本发明涉及集成电路器件的特性，更具体地说，涉及一种用于在FET器件的阈值电压特性中监测不可接受的扭结行为的改进方法，这可能是由于栅极氧化物厚度减小和衬底掺杂浓度降低引起的 沿着由STI界定的频道区域的长度。 这是通过将一对漏极电流与栅极电压特性作为衬底电压的两个值的函数来实现的。 在两个曲线之间的相对电压偏移在远低于扭结的漏极电流的值处以及远远高于扭结的漏极电流的值进行比较。 扭结行为的定量程度由对应于远低于扭结的漏极电流值的电压偏移量超过相应于低于扭结线圈的漏极电流的值的电压偏移量来确定多大。