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公开(公告)号：US08765546B1
公开(公告)日：2014-07-01
申请号：US13925812
申请日：2013-06-24
Applicant: United Microelectronics Corp.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Chih-Sen Huang
IPC: H01L27/088
CPC classification number: H01L21/823431
Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; forming a first gate structure on the fin-shaped structure; forming a first epitaxial layer in the fin-shaped structure adjacent to the first gate structure; forming an interlayer dielectric layer on the first gate structure and the first epitaxial layer; forming an opening in the interlayer dielectric layer to expose the first epitaxial layer; forming a silicon cap on the first epitaxial layer; and forming a contact plug in the opening.
Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板上形成翅片状结构; 在所述鳍状结构上形成第一栅极结构; 在与所述第一栅极结构相邻的所述鳍状结构中形成第一外延层; 在所述第一栅极结构和所述第一外延层上形成层间电介质层; 在所述层间电介质层中形成开口以暴露所述第一外延层; 在所述第一外延层上形成硅帽; 并在开口中形成接触塞。
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公开(公告)号：US20250048648A1
公开(公告)日：2025-02-06
申请号：US18916746
申请日：2024-10-16
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a magnetic tunneling junction (MTJ) on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes metal and the blocking layer includes a grid line pattern according to a top view.
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公开(公告)号：US20240365679A1
公开(公告)日：2024-10-31
申请号：US18205570
申请日：2023-06-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Jia-Rong Wu , Rai-Min Huang , Po-Kai Hsu
CPC classification number: H10N50/80 , H10B61/22 , H10N50/01 , G11C11/161
Abstract: The invention provides a semiconductor layout pattern, which comprises a first metal layer, wherein the first metal layer comprises a plurality of first patterns and a plurality of fishbone line patterns arranged on the same layer, wherein each fishbone line pattern comprises a principal axis pattern extending along a first direction and a plurality of branches arranged along a second direction, and each first pattern is located between two adjacent branches and the principal axis pattern, and a second metal layer is located on the first metal layer. A plurality of magnetic tunnel junction (MTJ) elements located on the second metal layer, wherein each magnetic tunnel junction element is arranged in a rhombic shape.
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公开(公告)号：US11800723B2
公开(公告)日：2023-10-24
申请号：US17019340
申请日：2020-09-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： I-Fan Chang , Hung-Yueh Chen , Rai-Min Huang , Jia-Rong Wu , Yu-Ping Wang
CPC classification number: H10B61/20 , G11C5/025 , G11C5/06 , G11C11/161 , H10N50/80
Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, a first gate pattern and a second gate pattern extending along the second direction adjacent to one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction adjacent to another side of the first contact plug.
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公开(公告)号：US20230247915A1
公开(公告)日：2023-08-03
申请号：US18132992
申请日：2023-04-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , Rai-Min Huang , I-Fan Chang , Ya-Huei Tsai , Yu-Ping Wang
Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.
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公开(公告)号：US20220392954A1
公开(公告)日：2022-12-08
申请号：US17888451
申请日：2022-08-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Jia-Rong Wu , I-Fan Chang , Rai-Min Huang , Ya-Huei Tsai , Yu-Ping Wang
IPC: H01L27/22 , G11C11/16 , H01F10/32 , H01F41/34 , H01L23/522 , H01L23/528 , H01L43/02 , H01L43/12
Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.
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公开(公告)号：US20180068951A1
公开(公告)日：2018-03-08
申请号：US15285471
申请日：2016-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Chih-Sen Huang
IPC: H01L23/535 , H01L23/528 , H01L27/092 , H01L21/768 , H01L21/8238 , H01L29/66
CPC classification number: H01L23/535 , H01L21/76805 , H01L21/76829 , H01L21/76895 , H01L21/823871 , H01L23/485 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/092 , H01L29/66545
Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.
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公开(公告)号：US09754938B1
公开(公告)日：2017-09-05
申请号：US15187800
申请日：2016-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Li-Wei Feng , Tong-Jyun Huang , Shih-Hung Tsai , Jia-Rong Wu , Tien-Chen Chan , Yu-Shu Lin , Jyh-Shyang Jenq
IPC: H01L27/088 , H01L29/06 , H01L21/8234 , H01L21/311 , H01L29/66
CPC classification number: H01L27/0886 , H01L21/31144 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L29/0649 , H01L29/66545
Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.
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公开(公告)号：US20170103896A1
公开(公告)日：2017-04-13
申请号：US15243986
申请日：2016-08-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Chih-Sen Huang , Chun-Hsien Lin
IPC: H01L21/28 , H01L21/285 , H01L29/49 , H01L29/78 , H01L29/06 , H01L29/66 , H01L21/768
CPC classification number: H01L21/28123 , H01L21/28088 , H01L21/28518 , H01L21/76805 , H01L21/76834 , H01L21/76837 , H01L21/76843 , H01L21/76855 , H01L21/76883 , H01L21/76895 , H01L21/76897 , H01L29/0653 , H01L29/4966 , H01L29/665 , H01L29/66545 , H01L29/66795 , H01L29/7851
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
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公开(公告)号：US09613969B2
公开(公告)日：2017-04-04
申请号：US14793714
申请日：2015-07-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ching-Wen Hung , Wei-Cyuan Lo , Ming-Jui Chen , Chia-Lin Lu , Jia-Rong Wu , Yi-Hui Lee , Ying-Cheng Liu , Yi-Kuan Wu , Chih-Sen Huang , Yi-Wei Chen , Tan-Ya Yin , Chia-Wei Huang , Shu-Ru Wang , Yung-Feng Cheng
IPC: H01L27/11 , H01L29/76 , H01L21/768 , H01L29/78 , H01L23/535 , H01L21/8234 , H01L21/311
CPC classification number: H01L21/823871 , H01L21/31144 , H01L21/76802 , H01L21/76805 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/823821 , H01L23/485 , H01L23/535 , H01L27/0922 , H01L27/1104 , H01L27/1108 , H01L29/7851 , H01L29/7853
Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
